Design flexibility and binning
The full-custom-design sensor, which offers a focal plane of 139.2x120mm, features 6.7-million (2800x2400) pixels on a 50-micron pitch and 32 analog outputs. It also features low noise, a high dynamic range and a programmable region of interest readout. Each pixel is constructed from a basic three-transistor (3T) base with a low-noise partially pinned photodiode, offering ‘charge-binning’ capability to deliver its high signal-to-noise characteristics. Pixel binning essentially combines a cluster of adjacent pixels into a single pixel. For example, in 2x2 binning, an array of four pixels becomes a single larger pixel, reducing the overall number of pixels available on the sensor. The sensor can offer a very high frame rate of 40 frames per second at full resolution and ‘binned’ images can be read at an increasingly faster rate. The high frame rate makes the sensor suitable for applications, such as digital tomosynthesis, that demand fast acquisition of multiple images. The design has a high degree of built-in flexibility: binning can be achieved on the sensor in both directions in steps of two or four. Binning also changes the effective pitch of the image to 100 or 200 microns from the fundamental 50-micron pixel pitch. Binning in the row direction also increases speed by at least a factor proportional to the binning factor.
Additionally, Region-Of-Interest (ROI) readout can be implemented. The ROIs can be programmed and the position of up to six ROIs can be stored on the sensor. High dynamic range can be achieved by reading the sensor multiple times. The timing information is also programmed and stored in the sensor before the start of a new image acquisition. Clearly, as the overall end-application sensor is stitched, it is fairly straightforward to generate a sensor with different number of pixels in either direction. And of course, the image sensor can be further redesigned with the modification of key parameters, depending on application demands.
Figure 2: A truly wafer-scale sensor, each unit requires a full 200mm wafer for its production.
Typical conventional Si-TFT (Thin-Film Transistor) is the current dominant technology used in digital-based X-ray imaging applications, which clearly has significantly fewer limitations in terms of panel size, but only offers limited performance characteristics including a frame rate of only a few frames per second maximum. Also, in comparison to the STFC sensor, other wafer-scale CMOS imagers currently being developed offer highly competitive readout performances, but in most cases do not come close in terms of frame rate. Overall, the STFC sensor offers a highly competitive combination of readout speed versus spatial resolution; both of these factors are crucial for digital tomosynthesis mammography. In addition to these advantages, the sensor provides noise significantly below 100 e-rms, whereas competitive imagers offer noise figures of well above 100 e-rms, some delivering more than 1000 e-rms.
Analog design and manufacturing
For the design of the sensor, the STFC group worked very closely with EDA Solutions, the sole representative for Tanner EDA in Europe. The designers used Tanner Tools Pro, in conjunction with Tanner’s HiPer Verify tool. The Tanner tools were extremely well suited for the complexity of the analog architecture in the design, and especially for the development of the innovative pixel-addressing IP, which was almost entirely analog circuitry with only a small amount of on-chip digital logic. Concerning the sensor’s production, the design group worked with TowerJazz which provided the 120x145mm image sensors (each using an entire 200mm silicon wafer for their production) based on its cutting-edge and high yield specialty 180/350-nanometer dual-gate CMOS Image Sensor (CIS) process technology. This CIS technology process enables the customization of pixels, according to project needs for many digital imaging applications, and offers excellent dark current, low noise and dynamic range performance characteristics. Importantly, the teams from the STFC, Tanner/EDA Solutions and TowerJazz have managed to achieve a first-right-time design with no prerequisite for any initial prototype design. Testing and full characterization of the sensor is now in progress.
About the authors:
is managing director of EDA Solutions -www.eda-solutions.com
He can be reached at firstname.lastname@example.org
Dr. Renato Turchetta
is CMOS Sensor Design Group Leader in the Rutherford Appleton Laboratory, Science and Technology Facilities Council (STFC) - www.stfc.ac.uk
He can be reached at email@example.com
Courtesy of EETimes Europe
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