In medical applications such as MRI, ultrasound, CT scanners, and digital X-ray, high channel count analog-to-digital converters (ADCs) are used to sample large arrays of data.
Serial interfaces are used to acquire the sampled data to reduce the number of pins on the ADC and FPGA, and save board space. With board real estate at a premium and FPGA pins a valuable commodity, the advantages of serial data converter interfaces over parallel are clear. Today, there are two choices of serial interfaces that are suitable for high speed data converters.
The first is a serial clock-data-frame (CDF) interface, which combines a serialized LVDS (low voltage differential signaling) data stream, as well as a differential clock to accurately collect this data and framing clock to establish data sample boundaries.
The second choice uses the JESD204 standard where the clock is embedded into a high speed gigabit-per-second (Gbps) two-wire serial data stream. Because of the higher power requirement of the current mode logic (CML) pairs used to drive the high speed JESD204 interface, serial LVDS is preferred for lower power, high channel count and portable designs. This article introduces some new serial LVDS ADC products from Linear Technology.
Serial LVDS output format reduces the number of digital I/O required between the ADC and FPGA, saving FPGA pins, board space and cost. In addition, by implementing a serial interface on the data converter, the number of pins required is greatly reduced, thus enabling smaller package sizes. This benefit is significant for high channel count designs. The choice of whether to use a serial LVDS interface over a parallel interface will depend on whether the application can tolerate the increase in power consumption, and whether the FPGA has the power to process the high speed data stream. The LTC2195, 16-bit 125Msps dual ADC with serial LVDS outputs has power dissipation of only 216mW per channel. However, the serial LVDS interface adds 31mW per channel over the dual parallel output version LTC2185 (Figure 1
). This family of 16-bit high speed ADCs offers excellent SNR performance of 76.8dB, as well as 90dB SFDR while offering very low power dissipation from a 1.8V supply.
Figure 1: Linear Technology’s 16-bit low power, high speed ADC family