As discussed previously, CE# must be low for all NAND activities. The
simplest NAND command is the Reset (FFh), which doesn't require any
address or second cycle. Simply assert CLE and issue a write pulse with
FFh on the data bus, and a Reset operation is performed. Reset is one of
two commands that can be issued while the NAND device is busy. If it's
busy processing a previous command, issuing a Reset aborts the previous
operation. Note that if the previous operation was an Erase or Program
command, issuing a Reset aborts the command prematurely, and the desired
operation doesn't complete. Because Erase and Program can be
time-consuming operations, they can be aborted with a Reset and
Read ID operation
The Read ID (90h) command requires one dummy address cycle (00h), but doesn't need a second command cycle (Table 1, again).
After issuing the command and dummy address, the ID data can be read
out by keeping CLE and ALE low and toggling the RE# signal for each byte
Read status operation
Read Status (70h) is the second command that can be issued while the
NAND device is busy. This command doesn't require an address or second
command cycle. The NAND device's status can be interrogated by issuing
the RE# clock signal. If the Read Status command is used to monitor the
device's ready state, the command should only be issued one time and the
status re-read by re-issuing the RE# clock. Alternatively, the RE#
signal can be kept low waiting for the appropriate status bit. Read
Status also includes the status of the write protect pin as well as the
pass/fail status of the previous Program or Erase operations. It's
mandatory that successful status be attained on Program or Erase
operations to ensure proper data integrity.
The Block Erase (60h) operation erases an entire block of 64 pages or
128 bytes total. To issue this operation, use the WE# signal to clock in
the Erase command (60h) with CLE asserted. Next, clock in three address
cycles, keeping ALE asserted for each address byte. The three address
cycles are the most significant address cycles of Table 2,
which includes the block and page addresses. The page address portion
(the low order 6 bits of the third address cycle) is ignored, and only
the block address portion of the three most significant bytes is used.
Once the address is input completely, issue the second command (command
cycle 2) of D0h, which also gets clocked in with WE# while CLE is being
asserted. This confirms the erase operation, and the device goes busy
for roughly 2 ms. When this operation completes, the device is ready for
another command. Notice the Read Status command can be issued at any
time, even when the device is busy during the erase. The processor or
controller could interrogate the device using the read status command.
Program operations can only program bits to 0, and assume that you
started with a previously-erased block. If you don't want to program a
bit, keep it in its erased state by setting that particular bit (or
group of bits) to 1. When the Program Page (80h) command is received,
the input register is reset to all 1s (internally). This lets the user
input only data bytes that he wants to program with 0 bits. The Program
operation starts with the 80h command, with CLE asserted (Fig. 4). Next, drop CLE and assert ALE to input the full five address cycles.
Click here for Fig. 4
Fig. 4. When the Program Page (80h) command is received, the
input register is internally reset to all 1s, letting the user input
only data bytes that he wants to program with 0 bits.
After the command and address are input, data is input to the register.
Once all the data has been input, we issue the confirm command (10h) and
start the programming operation. A Program operation typically requires
300 μs, although it may require up to 700 μs. It's mandatory that you
read the status and check for successful operation. If the operation
isn't successful, log the block and don't use it in the future. Move all
data from the block to a good block.