Toshiba, Samsung Meet Design Challenges
3 bit-per-cell and 4 bit-per-cell designs come with challenges. The first and most obvious issue is how to place the states with 8 different states for 3 bit-per-cell design and 16 different cell threshold voltage states in a cell in the case of 4 bit-per-cell design. From a circuit design standpoint, this means higher levels for internal voltage pumps to generate. Voltage pumps take a large portion of any NAND Flash die - even for MLC. With the requirement of generating higher voltage levels than before, voltage pumps for 3 bit-per-cell and 4 bit-per-cell NAND designs require higher efficiency and reliability, which are key factors for successful NAND product development.
Programming these 8 or 16 different states into individual a NAND Flash cell is critical in achieving high performance. ISSPP based programming methods have been widely used in MLC design in the past. New and innovative programming techniques presented in the latest NAND Flash designs have to be optimized for stability of operation and achieving reasonably performance required for the target applications. Increased NAND string size also affects how the word-line voltages are generated and applied to them depending on their relative position in a NAND string. DAC type voltage regulator control for inhibit voltage generator in the Intel and Micron's 34nm 32Gbit NAND Flash is an example. Improvements over 30% have been reported by Hynix with new programming algorithm called Start Bias Control and Smart Blind Program.
The programming performance of 3 bit-per-cell and 4 bit-per-cell NAND Flash designs varies from design to design but is generally at, or around, 5.5MB/s. Toshiba and SanDisk's 43nm 64Gb 4 bit-per-cell NAND shows 5.6MB/s. Hynix's 48nm 3 bit-per-cell 32Gb NAND Flash has 5.5MB/s. This is in contrast to the performance presented by Toshiba and SanDisk one year ago at ISSCC 2008 with their 56nm 3 bit-per-cell 16Gb NAND design having 8MB/s of performance. In case of Toshiba and SanDisk, despite the 4 bit-per-cell programming challenge and the increased NAND string size, the programming performance of 4 bit-per-cell NAND design shows fairly comparable performance with that of Hynix's 3 bit-per-cell design.
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To date, three 3 bit-per-cell NAND Flash designs have been reported in 56nm, 48nm, and 32nm process nodes. 2009 is the first year that the industry finally developed 4 bit-per-cell NAND Flash. This had been anticipated for many years since SanDisk's acquisition of MSystems in July of 2006. Given the challenges of placing 16 different states into smaller cells, the role of the embedded controller IC in NAND products will become even more critical for successful adoption of 4 bit-per-cell based NAND products in broader application areas.
NAND Flash memory industry has been under tremendous amount challenges from both technological innovation needs to overcoming scaling limitations as well as market challenges due to unfavorable pricing for the last couple of years. The resilience of this NAND industry, and perhaps the memory industry in general, comes from the amount and pacing of innovations that the designers and process/device engineers make every year to overcome seemingly insurmountable obstacles. Looking at the trend of cell efficiency of NAND Flash, one cannot help but notice the amount of improvements that the industry has made in the last 12 months. This is what keeps the industry going despite the cyclical nature of the memory market.