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Design Article

Micron drives process integration with 42-nm DDR3 SDRAM

Arabinda Das

5/10/2010 12:01 AM EDT

Expansion

The company expanded its partnership with fellow DRAM maker Nanya Technology Corp. and increased its manufacturing competitiveness. New technologies cannot be introduced quickly without innovation, so a strong R&D team and growing patent portfolio are important. In an ipIQ ranking of companies by corporate innovation (www.ipIQ.com), Micron has taken second place for two consecutive years, coming in closely behind Intel Corp.

Micron's 7x, 6x and 5x nodes all have similar process flows. The three previous nodes are all fabricated in a triple-metal, four-poly CMOS process with raised source/drain regions. The process uses copper damascene metal-3 and -2, tungsten metal-1, peripheral MOS transistors made of poly-1 with a tungsten clad layer, a TiN barrier, a nitrided gate oxide, shallow trench isolation with a nitride liner, and triple wells.

The SDRAM cell uses a stacked capacitor in a capacitor-over-bitline structure. The multilayer cell plate comprises poly, tungsten and TiN layers. The capacitor dielectric is a bilayer of high-k dielectric. The storage node is a TiN layer. Polysilicon landing plugs are used for capacitor contacts. A recessed channel array transistor (RCAT) with oxide dielectric is used in the SDRAM array to yield a longer effective channel length and lower channel doping concentration.

Micron's 4x node is similar in process but with some significant changes, particularly in the gate stack, interconnects and capacitor module. The capacitor height and the RCAT depth have not changed significantly. The gate dielectric thickness, the poly plug height and the contact width and pitch have been adjusted to accommodate scaling.

UBM TechInsights' full process analysis of the Micron 4x DDR3 DRAM discusses the changes in detail. For our purposes here, it is important to note that the 5x and 4x nodes are distinctly different from the 7x and 6x nodes, even though the process integration scheme is similar, because these last two nodes use advanced lithographic techniques, such as immersion and double patterning.

Even though major aspects of the processes are similar, from a design point of view scaling is still a challenge.





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