Winbond’s innovative DRAM design and the legacy of Qimonda

True innovations are relatively scarce in the manufacture and design of DRAM products. Due to razor-thin margins, DRAM manufacturers prefer to stick to well-known materials and conservative designs. Cost reductions are instead achieved by moving to smaller geometries at each new technology node, which allows an increase in memory density and the creation of more devices per wafer.

Examples of some of the major DRAM innovations that were adopted over the last few years include the 6F² cell architecture, the introduction of capacitor metal electrodes and zirconium-based high-k dielectric, and the recessed channel array transistor (RCAT). These improvements had such a profound impact on DRAM fabrication that they are now being used by virtually all the major DRAM companies in some form or another.

In a relative quietness, the Taiwanese manufacturer Winbond recently introduced their latest DDR2 products fabricated with a drastically different concept. The design, which could become as groundbreaking as the aforementioned technologies, is the buried metal wordline architecture. As the first manufacturer to mass produce this technology, Winbond received the prize for Most Innovative DRAM at the 9^th Annual Insight Award from UBM TechInsights.

The buried wordline concept explained

In a typical DRAM device, the bitline is formed in a metal level situated above the substrate, while the wordline is formed at the polysilicon gate level at the surface of the silicon substrate. In the buried wordline (bWL) architecture, the bitline is moved down to the poly level, while the wordline is formed within the substrate (i.e. in a trench) and made from a metal.

Figure 1: Cross-sectional image of the DRAM array showing the buried wordline.

The inherent advantages of this design are two-fold. Smaller parasitic capacitances between bitlines and wordlines compared to a conventional architecture result in lower power consumption and higher signal margin. The other advantage is due to the use of TiN metal gate for the array transistor. The metal gate results in a smaller electrical gate oxide thickness because of the absence of gate depletion, a higher on-current, and an overall faster cell access.

It must be noted that Winbond’s implementation of the buried wordline cell architecture is done at the 65nm node, which now represents a 2-year-old technology. For a new technology to be widely adopted in the industry, it must be able to scale down and retain its advantages even at the smaller dimensions. Earlier this year, Winbond announced that they were now developing the 46nm variant of the bWL technology. Considering that 4x-nm DRAM devices are already available in the market from major manufacturers, Winbond will probably be a year late in introducing their next node. However, the advantages of the bWL design may compensate for the lithography shortcomings.

The quest for 4F²

One of the lesser known benefits of the bWL design is that it possesses good compatibility with future 4F² architectures. All DRAM devices currently use at best a 6F² cell area, where F is the half-pitch of the wordlines or bitlines (which are the same in an optimized cell design). To achieve a higher memory density, two approaches are possible:

1-      Reduce F by adopting more advanced lithography techniques and smaller technology nodes (which is the most common way) or

2-      Reduce the coefficient of F² by adopting a different cell architecture.

The move from the conventional 8F² to the 6F² cell was done with relative ease. It was achieved by implanting an open bitline architecture while minimizing the isolation space between the cells as much as possible.

The change to a 4F² cell is, however, more complex, especially in the case of a DRAM device. The challenge lies in the fact that a DRAM cell contains one array transistor and one capacitor. In a standard stack capacitor device, the capacitor is a vertical, straw-like structure that minimizes its lateral footprint as much as possible. However, a transistor organized in a two-dimensional array and contacted by a bitline essentially occupies a 4F² area by definition (1 wordline pitch x 1 bitline pitch). The problem then consists of trying to fit a capacitor and a transistor in the area essentially occupied by a single transistor.

This is where the bWL architecture may have a significant advantage over the competition. The array transistor gate (i.e. the buried wordline) can almost be formed below the capacitor and bitline contact, thus saving precious cell real estate. Currently, the Winbond device uses a 6F² architecture with dummy wordlines to isolate adjacent cell nodes. This design, reminiscent of Micron’s own 6F² cell implementation, could potentially lead to a 4F² cell by eliminating the isolation wordlines. UBM TechInsights has prepared a full Memory Detailed Structural Analysis Report on the Winbond device.

Fig. 2: Winbond 6F² cell array layout at the polysilicon level.

The legacy of Qimonda

In all fairness, a substantial part of the Most Innovative DRAM prize should have been bestowed upon Qimonda. Qimonda was the memory company split out of Infineon Technologies that became the second largest DRAM manufacturer at its peak in 2007. The German company was first in introducing the buried wordline concept to the world at the end of 2008, but filed for bankruptcy protection soon after at the beginning of 2009.

Qimonda was well known for using a trench DRAM technology which consisted of forming the memory capacitor deep within the semiconductor substrate. However, at smaller dimensions, it became apparent that the trench technology was not going to be compatible with the recessed channel array transistor, which was now essential for reducing excessive cell leakage. Qimonda worked hard at developing and ramping up a 46nm stack capacitor DRAM with buried wordline technology at the end of 2008 and beginning of 2009, but ultimately did not have enough time to deliver a single stacked capacitor memory device to the market.

Today, Winbond of Taiwan is manufacturing both trench capacitor (90nm) and stacked capacitor (65nm) DRAM products based on the technology licensed from Qimonda. The fact that Winbond is now believed to achieve some of the best gross margins in the DRAM market is certainly a testament to the skills and ingenuity of the ex-Qimonda engineers.