Design Article
PCM The Myth of Scalability Part 3- Is WAL-PCM the salvation?
Ronald Neale
12/6/2010 9:59 AM EST
My original concerns with the ability of phase change memory (PCM) to scale to the sub 30nm lithographic nodes were directed principally at the problem of high current density and its consequences. A recent statement [1] and [2] has added new fuel to the PCM scalability argument, and it raised a new set of PCM scaling problems related to fabrication difficulties and power dissipation.
These new problems first appeared in a justification statement made as part of a patent application by some who are close to leading-edge PCM developments. Clearly, the purpose of the patent was to offer some new direction of development as a potential solution to the set of problems raised. This possible new direction for PCM structure will be explored in this article.
In Figure 1 (right-hand side is an artist’s impression of the newly proposed structure, in part cutaway), the active material is deposited as a sub-lithographic thin film on the sidewalls of a pore-like cylindrical aperture. This forms the active material into a tube, with the center of the tube back-filled with dielectric. At the bottom of the tube, the crystallized active memory material makes direct contact via an interface layer with a matrix selection device of the same diameter. The memory device acts as a "high aspect ratio" structure, with all of the thermal design advantages of that structure as was discussed in [3]. That is, the design keeps the cooling effects of the electrodes away from the active region and minimizes reset power.
My view of how this new PCM structure can be considered a close relative and evolved from the "link," is shown in the structural evolution diagrams at the right of Figure 1. These show that this new structure is, in reality, a rolled up or wrapped around link-PCM (WAL-PCM).
Next: Predicting Performance
These new problems first appeared in a justification statement made as part of a patent application by some who are close to leading-edge PCM developments. Clearly, the purpose of the patent was to offer some new direction of development as a potential solution to the set of problems raised. This possible new direction for PCM structure will be explored in this article.
In Figure 1 (right-hand side is an artist’s impression of the newly proposed structure, in part cutaway), the active material is deposited as a sub-lithographic thin film on the sidewalls of a pore-like cylindrical aperture. This forms the active material into a tube, with the center of the tube back-filled with dielectric. At the bottom of the tube, the crystallized active memory material makes direct contact via an interface layer with a matrix selection device of the same diameter. The memory device acts as a "high aspect ratio" structure, with all of the thermal design advantages of that structure as was discussed in [3]. That is, the design keeps the cooling effects of the electrodes away from the active region and minimizes reset power.
Figure 1: The Wrap Around Link (WAL-PCM) and its evolution. (Click figure for larger image.)
My view of how this new PCM structure can be considered a close relative and evolved from the "link," is shown in the structural evolution diagrams at the right of Figure 1. These show that this new structure is, in reality, a rolled up or wrapped around link-PCM (WAL-PCM).
Next: Predicting Performance
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janine.love
12/6/2010 10:13 AM EST
Editor's Note: We recently published what apparently was an extremely interesting statement with respect to a patent application and problems associated with phase change memory (PCM). The article and comments added further to the scalability questions already under discussion on the Memory Designline and EETimes. To explore this issue further, we asked Ron Neale to provide his view on if there might be any merit in the new patent and its associated structure. This is his response.
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Volatile Memory
12/6/2010 12:13 PM EST
Thank you for publishing Mr. Neale's analysis. Succint, yet sharp and devastating. The silence from Numonyx, Samsung, and IBM is deafening.
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resistion
12/6/2010 10:27 AM EST
The diagram graphics are impressive as always. I think one issue with this WAL structure is the fabrication. It looks like some ring-shaped mask is used to etch the structure. The etch damage to PCM especially so thin is a well-published phenomenon. The design might be good, but the execution may not go through as desired.
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R G.Neale
12/6/2010 11:05 AM EST
Resistion-I think, at say the 32nm process node they would cut a 20nm sub-lithographic pore in the dielectric then deposit a 3nm film of GST. Back fill the central core using a dielectric film deposition over the GST then chemically mill flat and deposit the upper electrode. Easier said (writ)than done, especially the circular sub-lith work, I agree.
Please do not take my artist's impression too literally, it is more to justify the use of link results in the analysis technique and the new name WAL-PCM.
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resistion
12/6/2010 2:00 PM EST
I agree, deposition would be better. But deposited 3 nm vs. say 50 nm GST can be very different behaviors. The interface with the thin GST would likely dominate over bulk predictions.
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Volatile Memory
12/6/2010 3:48 PM EST
Apparently, Samsung lied during the International Electron Device Meeting (IEDM) keynote again:
http://www.eetimes.com/electronics-news/4211282/Samsung--Six-challenges-seen-in-IC-scaling-
"PRAM is now being adopted in mobile phone applications as a code storage memory. The advantage of PRAM is that it can be scaled down to the 15 nm node and beyond."
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resistion
12/7/2010 12:18 AM EST
That is a quote from the paper. He had different emphasis in the presentation. It was no longer on PCM or STT, but on 3D NAND (and 3D versions of other technologies, incl. ReRAM). However, ReRAM is very early stage, compared to PCM. You should be aware, Samsung works on a lot of different, almost self-competing technologies at the same time.
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Volatile Memory
12/7/2010 12:45 AM EST
resistion: The strength and scope of Samsung's capabilities and research efforts are not a secret. However, the two sentences I quoted are false and misleading and Samsung has no excuse.
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R G.Neale
12/7/2010 6:03 AM EST
Truth or lies, if the E2550 phone with the PCM (see EETimes) did actually originate from Samsung then there was some truth in the statement of Samsung's Kinam Kim at IEDM2010. I recently added a comment my own comment to the EETimes piece on the finding of the PCM in the E2550 phone. It would appear that my prediction on the way the appearance of the PCM phone might be used by Samsung, at ISSCC2011, was fulfilled almost to the word at IEDM.
To me, more important than scoring points, when senior Samsung representatives make comments like “ PCM will scale to the 15nm node and beyond” it would be useful if they would indicate the current density they think will be involved and the structure. If Kinam Kim is using ITRS forecasts, I think they are based on the PCM dome heater electrode structure-the very structure with the heater that the WAL-PCM patent discussed above in PCM myth Part 3 teaches us it is too difficult to fabricate. Current density numbers for PCM pore at sub 30nm lithographic extracted from recent IBM paper on PCM at VLSI2010, down to 20 nm indicate over the contact diameter (CD) 70 to 20nm the current density would appear to be 2.8x10E7A/sq-cm (+/-0.1). I would be tempted to suggest, in accordance with the prediction of the PCM Myth Part 1, that this is flat and a minima. Best case downward extrapolation of that data to 15nm node with pore contact diameter (CD) of say 12nm is not likely to provide much of a reduction in current density. So perhaps they (Samsung) are planning to use the link structure “beyond” those dimensions! Whatever the structure, a need to know in fine detail what happens to molten GST at the current densities of a cathode arc spot (see E Hantzche 2006) is urgent as is the unified model of PCM operation.
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resistion
12/7/2010 11:11 AM EST
When Intel made the statement a few years ago that PCM was scalable to 5 nm (which I think is more aggressive than Samsung's 15 nm), they were referring only to using a probe tip to excite the phase change, as the demonstration. I think it doesn't mean directly translating to a 5 nm connected random access device. Likewise, probably most PCM studies are established with 15 nm and thicker films. I don't think phase change happening as low as 5 nm can be justified to say PRAM can scale to 15 nm and beyond. There are other considerations not related to the memory as well. Such as will the signal travel to an adjacent line before the memory cell?
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Volatile Memory
12/8/2010 5:38 PM EST
Somobody just brought to my attention an interesting document prepared by Samsung on October 4th, 2010:
http://www.samsung.com/global/business/semiconductor/support/brochures/downloads/memory/MobileMemory_brochure.pdf
Page 3 states: "Samsung’s 512Gb PRAM is combined with Mobile DRAM to deliver performance three times faster than NOR-based MCPs, making it ideal to quickly process large-size multimedia
files."
The "three times faster" is obviously a lie, but hard to prove given that the only PRAM chip in a cell phone has been destroyed.
However, it is obvious that Samsung lied about PRAM being 512Gb. It is just 512Mb. Samsung exaggerated by a factor of 1024x.
And, apparently, nobody has noticed so far. People must be busy installing those chips into fake phones instead of reading marketing materials.
Great job, Samsung!
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R G.Neale
12/9/2010 1:45 PM EST
Volatile Memory-I think that is most likely a translation or typographical error on the part of Samsung or their brochure editors. Most of us are aware where Samsung are in terms of PCM bit density in products. They are almost certain to be referring to their 512Mb PCM. I am sure they will correct it if and when they are made aware of it.
I think the next important PCM benchmark for Samsung is ISSCC2011 in February next year. With the burning question, will their paper be followed by a 1G-bit PCM product announcement? Or will it just record a notable PCM technological Tour de Force at 58nm. In a similar vein to the Multilevel Cell PCM that was presented by STM at ISSCC2008. Whatever it is, for me it will be nice to know for the 1 G-bit the PCM contact diameter and reset current density and write/erase lifetime for my records.
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Volatile Memory
12/9/2010 3:34 PM EST
R G.Neale: Apparently, Samsung carefully reads your stuff. They have now removed that unfortunate 512Gb marketing brochure, even though I did not contact them. Somebody there must be in a panic mode. With Flash prices dropping again and Spansion out with their 2Gb NOR at 65nm, Samsung must know their window of opportunity is rapidly shrinking.
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