Design Article
PCM The Myth of Scalability Part 3- Is WAL-PCM the salvation?
Ronald Neale
12/6/2010 9:59 AM EST
Finding Limits
The limit, in terms of diameter, will be when 2t = d. At that diameter, the WAL structure reverts to a conventional pore structure and will have similar electrical characteristics to it in relation to current density, offering no particular advantage over it. Consider the structure reducing in diameter to the extreme example when the diameter of the wrap around is 10nm and the active material thickness is 5nm, a conventional “pore” structure device will be the result. In that state, any consideration of equivalent link will lose its validity. The thicker link structures have been ignored for this analysis because as they reach the d =2t condition, they become pore devices at diameters of 40nm and 20nm
It is apparent from the two WAL-PCM characteristic curves (straight lines) shown in Figure 2, for devices using 3nm and 5nm thick films of active material, the current density remains in the region of 1x10E8 amps/sq-cm. This raises the question of what actually happens to molten chalcogenide when it is subjected to current densities at, or in this case close to that level. I believe that it is the detailed answer to that question that is the key to the to the scaling potential of PCM.
My analysis did not consider the thermal benefit of radiation in the dull red wavelengths (acting to thermally couple in a radial direction across the dielectric plug when the device is very small). If such thermal cross coupling (radiation or even conduction) occurs, it might improve the efficiency of the structure and result in beneficial deviation from the constant current density characteristics of the WAL structure to lower values. If this is the case, then it is likely to occur at values of diameter that will either not be practical or be little different from conventional pore structures.
Even if the effect of cross coupling does reduce the current density in any significant way, the current density for high-aspect-ratio pore devices is known. For example, the current density values quoted in [3] for conventional high-aspect-ratio pore devices at 50nm diameter were on the order 2x10E7A/sq-cm, a value below that predicted here in Figure 2 for a realistic WAL-PCM device at 20nm diameter with a 3nm thickness of active material. If the current density does deviate from the WAL-PCM straight line characteristics in a beneficial manner, as the devices are made smaller at the d = 2t, the end point of the straight line will still be the current density for the conventional high aspect ratio pore structure.
If the active material is thinned down, another important WAL structure consideration is the resistance of the cylinder of crystallized active material, acting as an electrode, which now appears in series with the active region. It has already been reported that attempts to make conventional high-aspect-ratio pore devices have had the on-to-off resistance ratio compromised by this effect. Pore devices do not have the central core region absent. This means that for one, or both, of the reasons above, fabricating devices close to the 2t =d region is not likely to be very productive in terms of the gains made.
In a more positive vein, the upper axis in Figure 2 is marked with three arrows for positions of WAL devices at diameters of 10nm, 20nm, and 30nm. The arrows point down to values of current density at equivalent link (Ew) widths on both the green and orange curves. These values are based on the external diameter and will move to the left if the mid-point (d-t) diameter is used, without any change in current density. For the 20nm diameter WAL device with a 3nm active material, the ratio of (d/t) is about 30, while for the 30nm diameter device the ratio is about 60. It is less for 5nm thick active films, but acceptable. Ratio values are large enough to suggest that the current density characteristics would be similar to a very wide link and be correctly located on the green and orange curves in Figure 2. With respect to the 10nm arrow, while it has marginal validity in predicting the current density for the 3nm thickness of active (i.e. d/t = 3.3), it has no validity with respect to the 5nm thick active material. It represents the d =2t condition, it is a pore.
Conclusion
From this analysis, it does not appear likely that even given some thermal engineering and the use of different passive materials, this new WAL-PCM structure will offer a solution to PCM scaling problems. Especially with respect to reliability questions raised regarding the operation of PCMs and associated devices and materials at current densities of the order 1 x 10E8A/sq-cm.
It does not offer a salvation to the PCM scaling problem as it relates to significantly reducing current density. However, creating a structure with the isolation device co-axial with and of the same diameter as the PCM structure is attractive, as is the possible use of silicon-on-insulator (SOI) for PCM applications.
For me, questions will remain about the future of PCM until there is a unified model of the operation of PCM that links the key variables of: current density, electro-migration, composition changes, write/ erase lifetime, and elevated temperature data retention. It must also address all of the lesser variables relating to device operation, pulse widths, rise times, on/off ratios and the like. If there is to be a significant PCM future, these are the areas where the effort must now be applied.
References
[1] EETimes PCM the Myth Part 2.
[2] US Patent Application 2010/078619, Statement #016, Redaelli et al.
[3] EETimes PCM Scalability-Myth or realistic device projection.
The limit, in terms of diameter, will be when 2t = d. At that diameter, the WAL structure reverts to a conventional pore structure and will have similar electrical characteristics to it in relation to current density, offering no particular advantage over it. Consider the structure reducing in diameter to the extreme example when the diameter of the wrap around is 10nm and the active material thickness is 5nm, a conventional “pore” structure device will be the result. In that state, any consideration of equivalent link will lose its validity. The thicker link structures have been ignored for this analysis because as they reach the d =2t condition, they become pore devices at diameters of 40nm and 20nm
It is apparent from the two WAL-PCM characteristic curves (straight lines) shown in Figure 2, for devices using 3nm and 5nm thick films of active material, the current density remains in the region of 1x10E8 amps/sq-cm. This raises the question of what actually happens to molten chalcogenide when it is subjected to current densities at, or in this case close to that level. I believe that it is the detailed answer to that question that is the key to the to the scaling potential of PCM.
My analysis did not consider the thermal benefit of radiation in the dull red wavelengths (acting to thermally couple in a radial direction across the dielectric plug when the device is very small). If such thermal cross coupling (radiation or even conduction) occurs, it might improve the efficiency of the structure and result in beneficial deviation from the constant current density characteristics of the WAL structure to lower values. If this is the case, then it is likely to occur at values of diameter that will either not be practical or be little different from conventional pore structures.
Even if the effect of cross coupling does reduce the current density in any significant way, the current density for high-aspect-ratio pore devices is known. For example, the current density values quoted in [3] for conventional high-aspect-ratio pore devices at 50nm diameter were on the order 2x10E7A/sq-cm, a value below that predicted here in Figure 2 for a realistic WAL-PCM device at 20nm diameter with a 3nm thickness of active material. If the current density does deviate from the WAL-PCM straight line characteristics in a beneficial manner, as the devices are made smaller at the d = 2t, the end point of the straight line will still be the current density for the conventional high aspect ratio pore structure.
If the active material is thinned down, another important WAL structure consideration is the resistance of the cylinder of crystallized active material, acting as an electrode, which now appears in series with the active region. It has already been reported that attempts to make conventional high-aspect-ratio pore devices have had the on-to-off resistance ratio compromised by this effect. Pore devices do not have the central core region absent. This means that for one, or both, of the reasons above, fabricating devices close to the 2t =d region is not likely to be very productive in terms of the gains made.
In a more positive vein, the upper axis in Figure 2 is marked with three arrows for positions of WAL devices at diameters of 10nm, 20nm, and 30nm. The arrows point down to values of current density at equivalent link (Ew) widths on both the green and orange curves. These values are based on the external diameter and will move to the left if the mid-point (d-t) diameter is used, without any change in current density. For the 20nm diameter WAL device with a 3nm active material, the ratio of (d/t) is about 30, while for the 30nm diameter device the ratio is about 60. It is less for 5nm thick active films, but acceptable. Ratio values are large enough to suggest that the current density characteristics would be similar to a very wide link and be correctly located on the green and orange curves in Figure 2. With respect to the 10nm arrow, while it has marginal validity in predicting the current density for the 3nm thickness of active (i.e. d/t = 3.3), it has no validity with respect to the 5nm thick active material. It represents the d =2t condition, it is a pore.
Conclusion
From this analysis, it does not appear likely that even given some thermal engineering and the use of different passive materials, this new WAL-PCM structure will offer a solution to PCM scaling problems. Especially with respect to reliability questions raised regarding the operation of PCMs and associated devices and materials at current densities of the order 1 x 10E8A/sq-cm.
It does not offer a salvation to the PCM scaling problem as it relates to significantly reducing current density. However, creating a structure with the isolation device co-axial with and of the same diameter as the PCM structure is attractive, as is the possible use of silicon-on-insulator (SOI) for PCM applications.
For me, questions will remain about the future of PCM until there is a unified model of the operation of PCM that links the key variables of: current density, electro-migration, composition changes, write/ erase lifetime, and elevated temperature data retention. It must also address all of the lesser variables relating to device operation, pulse widths, rise times, on/off ratios and the like. If there is to be a significant PCM future, these are the areas where the effort must now be applied.
References
[1] EETimes PCM the Myth Part 2.
[2] US Patent Application 2010/078619, Statement #016, Redaelli et al.
[3] EETimes PCM Scalability-Myth or realistic device projection.
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janine.love
12/6/2010 10:13 AM EST
Editor's Note: We recently published what apparently was an extremely interesting statement with respect to a patent application and problems associated with phase change memory (PCM). The article and comments added further to the scalability questions already under discussion on the Memory Designline and EETimes. To explore this issue further, we asked Ron Neale to provide his view on if there might be any merit in the new patent and its associated structure. This is his response.
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Volatile Memory
12/6/2010 12:13 PM EST
Thank you for publishing Mr. Neale's analysis. Succint, yet sharp and devastating. The silence from Numonyx, Samsung, and IBM is deafening.
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resistion
12/6/2010 10:27 AM EST
The diagram graphics are impressive as always. I think one issue with this WAL structure is the fabrication. It looks like some ring-shaped mask is used to etch the structure. The etch damage to PCM especially so thin is a well-published phenomenon. The design might be good, but the execution may not go through as desired.
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R G.Neale
12/6/2010 11:05 AM EST
Resistion-I think, at say the 32nm process node they would cut a 20nm sub-lithographic pore in the dielectric then deposit a 3nm film of GST. Back fill the central core using a dielectric film deposition over the GST then chemically mill flat and deposit the upper electrode. Easier said (writ)than done, especially the circular sub-lith work, I agree.
Please do not take my artist's impression too literally, it is more to justify the use of link results in the analysis technique and the new name WAL-PCM.
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resistion
12/6/2010 2:00 PM EST
I agree, deposition would be better. But deposited 3 nm vs. say 50 nm GST can be very different behaviors. The interface with the thin GST would likely dominate over bulk predictions.
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Volatile Memory
12/6/2010 3:48 PM EST
Apparently, Samsung lied during the International Electron Device Meeting (IEDM) keynote again:
http://www.eetimes.com/electronics-news/4211282/Samsung--Six-challenges-seen-in-IC-scaling-
"PRAM is now being adopted in mobile phone applications as a code storage memory. The advantage of PRAM is that it can be scaled down to the 15 nm node and beyond."
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resistion
12/7/2010 12:18 AM EST
That is a quote from the paper. He had different emphasis in the presentation. It was no longer on PCM or STT, but on 3D NAND (and 3D versions of other technologies, incl. ReRAM). However, ReRAM is very early stage, compared to PCM. You should be aware, Samsung works on a lot of different, almost self-competing technologies at the same time.
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Volatile Memory
12/7/2010 12:45 AM EST
resistion: The strength and scope of Samsung's capabilities and research efforts are not a secret. However, the two sentences I quoted are false and misleading and Samsung has no excuse.
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R G.Neale
12/7/2010 6:03 AM EST
Truth or lies, if the E2550 phone with the PCM (see EETimes) did actually originate from Samsung then there was some truth in the statement of Samsung's Kinam Kim at IEDM2010. I recently added a comment my own comment to the EETimes piece on the finding of the PCM in the E2550 phone. It would appear that my prediction on the way the appearance of the PCM phone might be used by Samsung, at ISSCC2011, was fulfilled almost to the word at IEDM.
To me, more important than scoring points, when senior Samsung representatives make comments like “ PCM will scale to the 15nm node and beyond” it would be useful if they would indicate the current density they think will be involved and the structure. If Kinam Kim is using ITRS forecasts, I think they are based on the PCM dome heater electrode structure-the very structure with the heater that the WAL-PCM patent discussed above in PCM myth Part 3 teaches us it is too difficult to fabricate. Current density numbers for PCM pore at sub 30nm lithographic extracted from recent IBM paper on PCM at VLSI2010, down to 20 nm indicate over the contact diameter (CD) 70 to 20nm the current density would appear to be 2.8x10E7A/sq-cm (+/-0.1). I would be tempted to suggest, in accordance with the prediction of the PCM Myth Part 1, that this is flat and a minima. Best case downward extrapolation of that data to 15nm node with pore contact diameter (CD) of say 12nm is not likely to provide much of a reduction in current density. So perhaps they (Samsung) are planning to use the link structure “beyond” those dimensions! Whatever the structure, a need to know in fine detail what happens to molten GST at the current densities of a cathode arc spot (see E Hantzche 2006) is urgent as is the unified model of PCM operation.
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resistion
12/7/2010 11:11 AM EST
When Intel made the statement a few years ago that PCM was scalable to 5 nm (which I think is more aggressive than Samsung's 15 nm), they were referring only to using a probe tip to excite the phase change, as the demonstration. I think it doesn't mean directly translating to a 5 nm connected random access device. Likewise, probably most PCM studies are established with 15 nm and thicker films. I don't think phase change happening as low as 5 nm can be justified to say PRAM can scale to 15 nm and beyond. There are other considerations not related to the memory as well. Such as will the signal travel to an adjacent line before the memory cell?
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Volatile Memory
12/8/2010 5:38 PM EST
Somobody just brought to my attention an interesting document prepared by Samsung on October 4th, 2010:
http://www.samsung.com/global/business/semiconductor/support/brochures/downloads/memory/MobileMemory_brochure.pdf
Page 3 states: "Samsung’s 512Gb PRAM is combined with Mobile DRAM to deliver performance three times faster than NOR-based MCPs, making it ideal to quickly process large-size multimedia
files."
The "three times faster" is obviously a lie, but hard to prove given that the only PRAM chip in a cell phone has been destroyed.
However, it is obvious that Samsung lied about PRAM being 512Gb. It is just 512Mb. Samsung exaggerated by a factor of 1024x.
And, apparently, nobody has noticed so far. People must be busy installing those chips into fake phones instead of reading marketing materials.
Great job, Samsung!
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R G.Neale
12/9/2010 1:45 PM EST
Volatile Memory-I think that is most likely a translation or typographical error on the part of Samsung or their brochure editors. Most of us are aware where Samsung are in terms of PCM bit density in products. They are almost certain to be referring to their 512Mb PCM. I am sure they will correct it if and when they are made aware of it.
I think the next important PCM benchmark for Samsung is ISSCC2011 in February next year. With the burning question, will their paper be followed by a 1G-bit PCM product announcement? Or will it just record a notable PCM technological Tour de Force at 58nm. In a similar vein to the Multilevel Cell PCM that was presented by STM at ISSCC2008. Whatever it is, for me it will be nice to know for the 1 G-bit the PCM contact diameter and reset current density and write/erase lifetime for my records.
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Volatile Memory
12/9/2010 3:34 PM EST
R G.Neale: Apparently, Samsung carefully reads your stuff. They have now removed that unfortunate 512Gb marketing brochure, even though I did not contact them. Somebody there must be in a panic mode. With Flash prices dropping again and Spansion out with their 2Gb NOR at 65nm, Samsung must know their window of opportunity is rapidly shrinking.
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