The limit, in terms of diameter, will be when 2t = d. At that diameter, the WAL structure reverts to a conventional pore structure and will have similar electrical characteristics to it in relation to current density, offering no particular advantage over it. Consider the structure reducing in diameter to the extreme example when the diameter of the wrap around is 10nm and the active material thickness is 5nm, a conventional “pore” structure device will be the result. In that state, any consideration of equivalent link will lose its validity. The thicker link structures have been ignored for this analysis because as they reach the d =2t condition, they become pore devices at diameters of 40nm and 20nm
It is apparent from the two WAL-PCM characteristic curves (straight lines) shown in Figure 2, for devices using 3nm and 5nm thick films of active material, the current density remains in the region of 1x10E8 amps/sq-cm. This raises the question of what actually happens to molten chalcogenide when it is subjected to current densities at, or in this case close to that level. I believe that it is the detailed answer to that question that is the key to the to the scaling potential of PCM.
My analysis did not consider the thermal benefit of radiation in the dull red wavelengths (acting to thermally couple in a radial direction across the dielectric plug when the device is very small). If such thermal cross coupling (radiation or even conduction) occurs, it might improve the efficiency of the structure and result in beneficial deviation from the constant current density characteristics of the WAL structure to lower values. If this is the case, then it is likely to occur at values of diameter that will either not be practical or be little different from conventional pore structures.
Even if the effect of cross coupling does reduce the current density in any significant way, the current density for high-aspect-ratio pore devices is known. For example, the current density values quoted in  for conventional high-aspect-ratio pore devices at 50nm diameter were on the order 2x10E7A/sq-cm, a value below that predicted here in Figure 2 for a realistic WAL-PCM device at 20nm diameter with a 3nm thickness of active material. If the current density does deviate from the WAL-PCM straight line characteristics in a beneficial manner, as the devices are made smaller at the d = 2t, the end point of the straight line will still be the current density for the conventional high aspect ratio pore structure.
If the active material is thinned down, another important WAL structure consideration is the resistance of the cylinder of crystallized active material, acting as an electrode, which now appears in series with the active region. It has already been reported that attempts to make conventional high-aspect-ratio pore devices have had the on-to-off resistance ratio compromised by this effect. Pore devices do not have the central core region absent. This means that for one, or both, of the reasons above, fabricating devices close to the 2t =d region is not likely to be very productive in terms of the gains made.
In a more positive vein, the upper axis in Figure 2 is marked with three arrows for positions of WAL devices at diameters of 10nm, 20nm, and 30nm. The arrows point down to values of current density at equivalent link (Ew) widths on both the green and orange curves. These values are based on the external diameter and will move to the left if the mid-point (d-t) diameter is used, without any change in current density. For the 20nm diameter WAL device with a 3nm active material, the ratio of (d/t) is about 30, while for the 30nm diameter device the ratio is about 60. It is less for 5nm thick active films, but acceptable. Ratio values are large enough to suggest that the current density characteristics would be similar to a very wide link and be correctly located on the green and orange curves in Figure 2. With respect to the 10nm arrow, while it has marginal validity in predicting the current density for the 3nm thickness of active (i.e. d/t = 3.3), it has no validity with respect to the 5nm thick active material. It represents the d =2t condition, it is a pore.
From this analysis, it does not appear likely that even given some thermal engineering and the use of different passive materials, this new WAL-PCM structure will offer a solution to PCM scaling problems. Especially with respect to reliability questions raised regarding the operation of PCMs and associated devices and materials at current densities of the order 1 x 10E8A/sq-cm.
It does not offer a salvation to the PCM scaling problem as it relates to significantly reducing current density. However, creating a structure with the isolation device co-axial with and of the same diameter as the PCM structure is attractive, as is the possible use of silicon-on-insulator (SOI) for PCM applications.
For me, questions will remain about the future of PCM until there is a unified model of the operation of PCM that links the key variables of: current density, electro-migration, composition changes, write/ erase lifetime, and elevated temperature data retention. It must also address all of the lesser variables relating to device operation, pulse widths, rise times, on/off ratios and the like. If there is to be a significant PCM future, these are the areas where the effort must now be applied.
 EETimes PCM the Myth Part 2
 US Patent Application 2010/078619, Statement #016, Redaelli et al.
 EETimes PCM Scalability-Myth or realistic device projection