Understanding and selecting higher performance NAND architectures

As NAND Flash process lithographies have decreased to the 30nm and 20nm classes, much higher NAND capacities have become available to meet ever increasing demand for higher density storage in applications from cameras to mobile phones, camcorders, industrial hand-held devices, solid-state drives, and more.  However, as capacities have increased, certain aspects of NAND performance have needed improvement, including a need to increase NAND data transfer rates.  As a result, memory manufacturers have developed new higher performance NAND architectures to address these issues, such as double data rate (DDR) NAND Flash.  Other solutions include NAND with built-in error correction code (ECC) to offload a portion of the host controller requirements, or NAND integrated with a complete controller, such as e-MMC NAND.

This article is intended to help system and memory subsystem designers understand the differences and benefits of some of the newer NAND architectures.

Performance challenges with increasing capacity
Accompanying the increase in capacities has been an increase in NAND page size, which is the amount of data that is read or written internally at one time.  While a larger page size allows a greater amount of data to be read or written in one command, it can also increase the data transfer time between the host and the internal data register.  

The total time required for a NAND read or write is determined by two elements: the NAND array access time, (tR  for read array access time or tPROG for program access time) and NAND data transfer time (tRC for reads or tWC for writes) between the host and the data register.  As page sizes have increased from 2kB to 8kB, the data transfer time has approximately quadrupled from 53µs to 219µs at the conventional transfer rate of 40 megatransfers per second (MT/s) [1].  

In order to reduce this data transfer time, DDR devices have been introduced in which two bytes are transferred per cycle.  DDR NAND solutions have been available in the market for some time, but to date, they account for a relatively small percentage of NAND shipments.  With the larger NAND chip densities now on the market, the performance improvement available from DDR becomes advantageous for high performance applications including solid state drives (especially those for enterprise applications), and mobile and consumer electronic applications where a stretch in performance is often in demand by consumers.  As a result, DDR NAND solutions are likely to become a larger percentage of the NAND mix in the future.



As NAND page sizes have increased from 2kB to 8kB with larger density chips, the total time for a NAND page read operation, which is comprised of the page read access time tR, and the and the data transfer time, has quadrupled in legacy NAND [2].  The data transfer time is the bottleneck, especially for the larger page sizes.


For the 8kB page size, at a data transfer speed of 133MT/s (e.g. Toggle Mode 1.0), the data transfer time is reduced to approximately one-third, and the total page read time is reduced to less than half.

Another aspect of increasing density and decreasing cell size is an increase in ECC requirements.  In traditional NAND implementations, the host controller handles NAND management functions, including block management, wear leveling and ECC.  As lithographies have increased, so have requirements for error correction, a requirement for both hard disk drives and NAND storage to ensure data integrity.  To address the challenges that increasing ECC requirements create for system manufacturers and controller manufacturers, NAND designs that include ECC on the NAND chip have been developed to offload this function from the host controller.