Understanding and selecting higher performance NAND architectures

DDR NAND
There are two major DDR NAND designs available in the market, Toggle Mode  from Samsung and Toshiba, and ONFI NAND, from the Open NAND Flash Interface (ONFI) Working Group , supported by several other NAND manufacturers including Hynix, Intel, Micron, SanDisk and Spansion.  Both types are supported by a wide range of software and third party controller manufacturers.  Today, efforts are underway in JEDEC to establish a common command set between these competing approaches to higher performance NAND with the overall objective of simplifying design-in of NAND Flash.  

ONFI  DDR NAND
The ONFI Working Group was formed in May 2006, dedicated to simplifying integration of NAND Flash into both consumer electronics and computing platforms.  Today, according to its website, the group has more than 90 members.  The primary factor driving the group’s efforts is that the use of NAND Flash is often hampered by lack of sufficient standardization.  To support a new NAND Flash component on a platform, host software and hardware changes are often required.  Implementing these changes can be costly, due to design changes and testing cycles.  The ONFI goal has been to develop a standardized interface design, with the objective of making it easier to design NAND Flash into new systems.  

NAND products compliant with ONFI NAND  v 1.0 specification were the first commercial DDR NAND, which defines a 50MT/s transfer rate, a twenty percent improvement over legacy NAND’s 40MT/s transfer rate.  In the second generation, ONFI 2.2, an asynchronous single data rate version was introduced, with a 50MT/s maximum transfer speed, while the maximum transfer speed for the synchronous DDR version increased to 200MT/s.  In the most recently announced specification, ONFI 2.3, a new error corrected EZ-NAND (ECC Zero NAND) was introduced in which the NAND device performs error correction and provides corrected data to the host.  The specification includes both MLC and SLC NAND, and defines a single data rate asynchronous device and a double data rate synchronous device with data transfer speeds that match those of ONFI  v 2.2.  A roadmap for ONFI v 3.0 has been announced, with a targeted interface speed of 400MT/s.


Toggle mode DDR NAND
Toggle Mode NAND, with products available from Samsung and Toshiba, was developed as an asynchronous double data rate NAND without a separate clock signal to enable a lower power solution than typical synchronous double data rate memory chip designs.  It also maintains many interface similarities to legacy NAND to help simplify system design.  Toshiba Toggle Mode v 1.0 NAND is offered in both Single Level Cell and Multi Level Cell versions.  

JEDEC standard Toggle Mode 1.0 DDR NAND has a fast interface rated at 133MT/s, compared to 40MT/s for legacy SLC single data rate NAND, to achieve approximately a three-fold increase in transfer speed.  Since it uses an asynchronous interface similar to that used in conventional NAND, the Toshiba DDR Toggle Mode NAND requires no clock signal, which means that it uses less power and has a simpler system design compared to competing synchronous NAND alternatives.  The bidirectional DQS signal that controls the read and write enable functions in Toggle Mode NAND only consumes power during a read or write operation.  In synchronous DDR NAND, the clock signal is continuous, and often uses more power.  It is not easy to quantify the power consumption difference more specifically, as it varies with the frequency and duration of the read and write operations.  


The DDR interface in Toggle Mode NAND uses a bidirectional DQS signal to control the data interface timing.  The DQS signal is driven by the host when it is writing data to the NAND and is driven by the NAND when the NAND is sending to the host.  Each rising and falling edge of the DQS signal is associated with a data transfer.  Toggle Mode NAND also has on-die termination to improve signal integrity.  Scalability to future high-frequency operation is enabled as well.  The next generation standard for Toggle Mode 2.0 defines a DDR NAND flash with a 400MT/s interface.  Toggle Mode DDR NAND 2.0 will provide approximately a three-fold increase in interface speed over Toggle DDR 1.0 and a ten-fold increase over the 40MT/s single data rate NAND in widespread use today.  

(Toshiba Toggle Mode NAND supports common legacy NAND commands including basic, multi-plane and cache operations.  Toshiba’s initial Toggle Mode DDR NAND 1.0 is available as MLC NAND in densities of 64Gb [3] 128Gb and 256Gb and SLC versions with densities of 32Gb, 64Gb and 128Gb.)