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Design Article

NAND 201: the continued evolution of NAND Flash

Jim Cooke, Micron Technology

2/13/2011 1:23 PM EST

A lot has changed with NAND Flash memory since my original NAND 101 article was published in 2006. From the evolutionary changes of a continually shrinking NAND cell, to the performance-enhancing innovations that support increasingly advanced designs, this follow-on article will chronicle the developments in NAND technology from 2006 through early 2011.

Market Changes
In 2006, single-level cell (SLC) NAND Flash devices were mainstream products that accounted for more than 80% of the devices on the market. At that time, many NAND Flash vendors were struggling with two bits per cell, known as multilevel cell (MLC), and SLC device densities were in the range of just a few gigabits. Today, for example, Micron offers a range of NAND products with densities up to 512Gb in a single device.

Figure 1 shows the past, present, and projected output mix for the major NAND cell technologies. The high runners are all MLC devices, which have replaced SLC devices in holding approximately 80% of the total market. While 16-level-cell technology grew to a few percent in 2010, it is expected to drop to 0% in 2011 due to the continued difficulty of reliably placing 16 discrete thresholds in a single cell. 8LC devices, which pack three bits per cell, are expected to grow from less than 10% in early 2009 to almost 30% by the end of 2011. These devices are used primarily in value-minded consumer products that can operate with lower NAND performance and fewer PROGRAM/ERASE cycles (also known as endurance). Traditional MLC devices, which group two bits (four levels) per cell, are ideal for applications that demand higher performance and endurance; thus, MLC drives the majority of NAND output. Lastly, SLC NAND is the technology of choice for high-performance, high-endurance, and high-reliability applications. Later, we will discuss some separate, specialized NAND devices that have been born out of necessity.


Figure 1:  NAND Production by Type (Click graphic for hi-res PDF)

Figure 2 shows the expected application adoption of 3-bit-per-cell (8LC) NAND devices. In addition to early drivers such as Flash cards and USB thumb drives, several other consumer application designs are expected to be based on this technology.



Figure 2:  8LC Density Adoptions by Application (Click graphic for hi-res PDF)


NAND Basic Operations
While the NAND cell itself has remained essentially the same over the last several years (albeit much smaller), almost everything else about NAND has changed (see Table 1; (Click graphic for hi-res PDF)).




janine.love

2/13/2011 6:50 PM EST

I recently asked Jim for this follow-up to his wildly popular NAND 101 article, and he graciously agreed. Hope you enjoy it. Thanks Jim.

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kinnar

2/15/2011 2:39 AM EST

It was a very kind suggestion, and this article talks very well about the NAND Memories.
I was expecting more adoption of 16LC devices but article talks that this will no more be in production as it is not reliable. So does it say that it will not be possible to have more storage on NAND? or does it limit the expandability of NAND Memories?

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Jim.Cooke

2/15/2011 8:34 AM EST

Hi Kinnar,
The reason 16LC has not developed as much as you would have expected is because it is very difficult. As the basic NAND cell continues to shrink, the total number of electrons available in each cell also shrinks. This makes it very difficult to store 16 levels reliably.

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katgod

2/16/2011 2:11 PM EST

Nice overview

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resistion

2/17/2011 12:32 PM EST

I think forward insights got it backwards. As smaller geometries emerge, mlc and 8lc become less viable, so slc should relatively grow.

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Dr DSP

2/17/2011 3:54 PM EST

Any thoughts on what happens to endurance as we go to smaller lithography? Can we expect dramatic changes?

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Jim.Cooke

2/27/2011 11:16 AM EST

We expect to see a continued reduction in endurance with each process shrink. However, with each process shrink, the densities are doubling. With the increased density, and proper wear leveling, the net result is about equal, to the user.

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MKC

2/17/2011 6:58 PM EST

With smaller geometries, do per page voltages (during reads and especially programs) decrease at some rate (relative to geometry reductions)? Or do they hover around ~5 and ~20V (ignoring selected or unselected page voltages)?

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TomTom_#1

2/23/2011 12:19 AM EST

Hi,

We need to store ECC information while writing data to NAND right.

My understanding is we are doing so because, some errors might occur while reading DATA from NAND.

What will happen if error occurs while reading NAND Spare Area. Is it guaranteed that no errors occur when we read from the Spare Area?

Thank You & Regards,
GSR

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richi777

3/3/2011 6:43 PM EST

ClearNand is a good product, similar to LBA-Nand from Toshiba.

Best regards !

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