System design using NAND flash memory

NAND flash error correcting code (ECC) has been on the rise since NAND was first introduced. Although it’s not a new issue, the ECC required to support newer multilevel (MLC) and three-bit-per-cell technologies is becoming increasingly difficult for system designers to keep up with. ECC has historically been used to improve the overall data reliability of NAND subsystems. However, as NAND cells shrink, fewer electrons are stored per floating gate. To compensate for the increasing bit error rates of these smaller geometry cells, ECC requirements have to dramatically increase to maintain the desired system reliability.  

As system requirements for ECC increase, the number of gates necessary to implement the logic also increases, as does the system complexity. For example, 24 bits of ECC requires about 200,000 gates, while 40 bits of ECC requires about 300,000 gates. It is estimated that in the future, advanced algorithms will approach close to 1 million gates -  see figure 1.

Figure 1: ECC increases as process geometries shrink.

Many high-performance flash systems require multiple channels of NAND to reach the desired performance. In these systems, each channel typically has its own ECC logic. For example, a 10-channel SSD may have  10 channels of ECC logic implemented. If 60 bits of ECC were required for each of the 10 channels, the result would be 3 million gates just for the ECC logic.

NAND interface choices
The NAND interface has traditionally been an asynchronous interface. Although interface speeds have improved up to 50 MHz in recent years, not much else has changed on this interface. Several years back, Micron and several other forward-thinking companies joined together to form a NAND flash organization that was focused on simplifying the myriad of timing and command specifications offered by the industry. The Open NAND Flash Interface (ONFI) developed the first version of their specification, ONFI 1.0. While there are many advantages to the original ONFI 1.0 specification, one
of the biggest is the ability for the host to electronically detect the type of flash device that is connected, as well as other  important parameters, like timing modes, page size, block size, ECC requirements. This feature  has been carried forward to all of the ONFI specifications and remains an important aspect of all ONFI standards.

Another significant accomplishment of the ONFI organization was the development of the synchronous NAND interface, also known as ONFI 2. ONFI 2.2 currently supports up to 200 mega transfers per second (200 MT/s) using a DDR, source-synchronous interface.  After powering up, it can be used in asynchronous mode.

However, for higher performance, the host can interrogate the flash device to see if it is able to support the higher-speed synchronous interface before changing to it.

This is an excerpt of an article that appeared in Electronic Engineering Times Europe, February 2011. You can download the complete article in PDF format.