Phase change memory (PCM) progress report, part 2

PCM progress risks at the sharp end
The CNT work of U of I-U was elevated to the top of the order for this progress report which, when originally planned, was intended to cover the hoped-for announcement of a 1G-bit product by Samsung, quickly after their ISSCC2011 presentation [8]. So far, at the time of writing, that has not happened.

In February 2011 at Micron’s presentation to analysts, two speakers provided the latest up-dates on PCM progress. The more detailed and optimistic presentation was from Mario Licciardello, VP of Micron’s Wireless Solutions Group who provided one gem of information regarding the Micron view of future products and sales uptake of PCM compared with NOR and NAND.
 

Figure 5: The predicted growth in PCM sales.

The PCM specific data has been reproduced in Figure 5. It shows measurable PCM unit sales starting in 2012 and building to 200 million units in 2013 and on to the order of 400 million units in 2014. The year 2014+ is also the year that IBM [9] predicted that PCM might first appear in their own servers; at least now it appears that they are all singing from the same PCM hymn sheet.

Figure 5 also shows that PCM growth will occur at the expense of NOR. Mario Licciardello presented a view that Micron possessed a device portfolio with the ability to serve all aspects of mobile wireless communication from entry level connectivity on up to smart phones and media tablets. At the moment, the role for PCM was PCM+LPDDR2 at entry level, in a multi-chip package, with the reality categorized as “in design and development” along with a shared bus application chipset to facilitate integration soon to be announced by another company. The path of PCM device development was linked to the convergence of  entry segment mobile communications into a single solution. It was suggested that, in the longer term, all three aspects of entry level: low cost, mainstream, and low-cost 3G, would converge on a PCM solution, where PCM-LPDDR2N and LPDDR2 components would operate on a shared bus.  This also appears to be claiming that such a solution would effectively eliminate the need for all of: NOR ADMUX+PSRAM; NOR+SDR/DDR; SLCNAND+SDR/ and oneNAND+DDR now used across the entry level. All of this provides a very tantalizing PCM raison d’etre, (or even reason for keeping the PCM project going).

What then of the PCM devices that will facilitate this convergence? Mario Liccarderelli, without offering timing except from that in Figure 5, indicated that there will be a need for 512 G-bit, 1G-bit and 2G-Bit PCMs all capable of operating with DDR800 x 16 interfaces, with the 2G-bit also having DDR800x32 capability.  To impress, one of the presentation slides displayed prominently what appeared to be a 45nm Numonyx/Micron 1G-bit PCM, now apparently relegated to “demonstration” status.

My interpretation of the product road map is that Micron (and/or competitors) will need to move from their present position of:  90nm 128Mbit serial/parallel PCM products and at least two 1G-bit 45nm demonstration devices, to both 1G-bit and 2G-Bit PCM products that are competitive in price and performance and also by 2013 have achieved a significant number of application design-ins.

What then is the likelihood that all of this will happen? In his presentation, Licciardelli indicated that he could see no short-term risks with respect to scalability. However, another speaker at the same presentation appeared to present a slightly different view of risk with respect to PCM and other leading-edge and competing non-volatile (NV)/universal memory technologies.

In his presentation, Mark Durcan, COO of Micron, produced a chart that offered a view of the elements of risk associated with key aspects of each of the new emerging NV memory technologies. A graphical representation of his data is reproduced shown in Figure 6. He allocated extreme risk to bit density (scaling) for PCM.


Figure 6: The risks associated with a mixture of parameters and activities for competing and emerging NV memories.


While Mark Durcan assigned four levels of relative risk to each new memory technology, we have assigned five in order to include zero risk. Implicit in such a simple chart is that all activities and device parameters listed and compared are given equal strength/weight as far as technical and business risks are concerned in achieving the desired objective. Therefore, in Figure 6 a “red” level of risk on “manufacturability” has the same weight as “red” on “endurance.” With that as a given, the inverse reciprocal of risk is probability of success. To obtain that probability, a weighting or strength must be assigned to each level of risk. (For the moment the complex matter of assigning accurate weights to cover business and technical risk will be left to others.) However, just assigning a simple linear weight to the risk boxes of Figure 6 would appear to indicate that CBRAM (the electro-chemical bridge-forming memory) and NAND have a higher probability of success in meeting the chosen goal than PCM. That might have important significance with respect to the future of PCM at Micron and the behind the scenes thinking. It is possible to have a high technical risk and a low business risk and keep any project running, as window dressing or for amortization purposes. The public position according to Mark Durcan is Micron is in the process of evaluating all possible candidate next-generation memory technologies by means of both internal evaluation and strategic alliances.