Phase change memory (PCM) progress report, part 2

Samsung
As stated earlier, it was hoped this report as originally planned would cover the announcement by Samsung of the 1G-bit PCM as a product after its presentation at ISSCC2011 [8]. Samsung’s 1G-bit device proved to be, as billed, more about the establishment of a LPDDR2-N interface for PCM (PRAM) and a few clever silicon design techniques to achieve a claimed 6.4MB/s bandwidth. This core-programming performance of 6.4MB/s utilized a data-comparison write with inversion flag (DCWI) scheme and a novel timing control method. For read, a mid-array pre-charge scheme was implemented.

For the 1G-bit, the technology node for the 1G-bit was held at 58nm, which is close to the value for the Samsung’s  512 M-bit PCMs available in product form. EETimes [11] carried PCM related report of comments at ISSCC2011 made by Oh-Hyun Kwon, President of the Samsung Electronics Co. Ltd semiconductor business. He said that it is still unclear how far today’s memory technology-such as DRAM, NAND and NOR-can scale. Samsung itself is developing a range of next-generation replacement technologies, such as 3-D NAND, MRAM, PRAM and ReRAM.

But there has been an overall reluctance by the systems houses to adopt the various next-generation memory technologies. He urged OEMs to collaborate more with the memory houses in order to get wider adoption for the next-generation memory types. Again, as with Micron, he took the broad brush approach to all leading-edge memory options. The reluctance of systems houses to adopt the new technologies, and because PCM is their major product offering in that respect, those words might well confirm a lack of significant sales of the 512M-bit PCM. A lack of sales and a lack of clarity on the ability of existing technologies to scale might well be the reason why there has not been an ISSCC2011 follow-up product announcement of a 1G-bit product from Samsung. It could also be the device did not perform as expected.

A clue to its disposition might be found elsewhere, in a presentation to be made by Charles (Chuck) Dennison COO, VP Ovonyx Inc  at MIT on 5th April 2011 [12]. Perhaps one should not ascribe too much to it, but one aspect of the promotional material is very interesting, it runs “In this time period, phase change memory has emerged as the leading alternative NVM PCM solution with shipments of 512 Mb products (by Samsung) and full demonstration of 1G-bit die by Ovonyx licensees surpassing by close to two orders of magnitude all other disruptive memory technologies.”  The use of the plural “licensees” might suggest that this includes the fate of Samsungs 1G-bit PCM, in that it has also been reduced to “demonstration” status. Thi is the word used by a Numonyx/Micron representative [13] to define the fate of the Numonyx-Micron inherited 45nm 1G-bit.

Conclusion
The work of Professor Pop on CNTs [2] is to be admired and is certainly what university departments should be paid to do. Producing a viable CNT-PCM technology that is monolithically integrated with conventional silicon will require dealing with the complexity of two foreign back end of the line (BEOL) processes, ignoring for the moment any problems associated with current density.  Alternatively if CNT technology can be used to provide a usable active device, with gain, it could be the basis of a new PCM-IC technology that solves the complex processing problems; however, at the moment, this is a very big "IF." For PCM, the use of CNT technology would appear to have a very long way to go, but for university departments the journey of CNT development is worthwhile and likely to yield many useful by-products.  It would appear that much of the early confidence that PCM technology would surpass all others is on the wane and being replaced with a broad-brush approach embracing all emerging NV memory technologies.   
 
References

[1] EETimes Academics scale PCM with carbon nanotubes Peter Clarke.
http://www.eetimes.com/electronics-news/4213997/Academics-scale-PCM-with-carbon-nanotubes


[2] Low-power switching of Phase-Change Materials with Carbon Nano Tube Electrodes, by Feng Xiong, Albert Liao, David Estrada and Prof Eric Pop. ScienceExpress 10th  March 2011.

[3]Voltage polarity effects in GST-based Phase Change Memory: Physical Origins and Implications, A Padilla, G W Burr et al. Proceedings IEDM10, p 656-659.

[4] EEtimes PCM Progress: Temperatures rise and constituents on the move.
http://www.eetimes.com/design/memory-design/4212344/PCM-Progress--Temperatures-rise-and-constituents-on-the-move

 
[5] Current status of the phase change memory and its future, by
Stefan Lai, Proc IEDM 2003

[6] Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb, sl Cho et al, Proc IEDM 2005.


[7]EETimes RGN PCM Scalability Myth
http://www.eetimes.com/design/memory-design/4206311/PCM-scalability-Myth-or-realistic-device-projection

[8] A 58nm 1.8v 1Gb pRaM with 6.4MB/s program BW by H. Chung, B. Jeong, B. Min et al, Samsung Electronics, Hwasung, Korea, Proceedings ISSCC 2011. 


[10] EETimes: IBM CTO confirms support and 2014 plus prediction



[11] EETimes Mark LaPedus: Samsung CEO: Headwinds hinder PRAM


[12] An MTL Seminar, Semiconductor Memory in the Driver’s Seat: Where are we headed? By Charles Dennison, VP of Ovonyx, Inc. 5th April at  4:00 PM, Edgerton Hall, Room 34-101. MIT.

[13] EETimes Ref to Numonyx/Micron 1G-bit as demonstration vehicle.    http://www.eetimes.com/electronics-news/4204946/Micron-Phase-Change-Memory