Design Article
Tell us What You Think
We want to know what you thought about this Design. Let us know by adding a comment.
The first CMOS embedded MTP NVM IP in 40nm – Itera
David Hsu, Kilopass Technology Inc.
4/26/2011 5:51 PM EDT
In recent years we have seen explosive growth in the usage of on-chip non-volatile memory (NVM) in high volume SoCs for TVs, PCs, and mobile devices. NVM stores a wide range of information, from encryption keys, trimming values, configuration settings, memory patching, to firmware (test code, boot code, and application code). Storing such data on-chip increases security, reduces the bill of materials (BOM) cost, shrinks board real estate, lowers power consumption, minimizes costs, cuts time-to-market (TTM), and increases reliability.
In many applications one-time programmable (OTP) memory is used, but there are other high-value applications requiring multi-time programmable (MTP) memory that can provide the ability for the device to be updated. For example, due to degradation from aging or changes in their operating environment, it may become necessary to re-calibrate and re-trim mixed signal circuits like high-performance DACs that are integrated in today’s complex SoCs. Other examples include access key revocation, upgrading to a new revision of code, and periodic data logging.
Two very common forms of MTP NVM are EEPROM and Flash, both of which are based on the concept of a floating gate. These technologies in the embedded form are available only in higher process nodes such as 180nm, 130nm, and 90nm, but they are not available at more advanced nodes. This is due to the fact that, as the floating gate and oxide layers become thinner, leakage issues render these technologies unreliable for long-term data retention. Consequently, with no embedded MTP NVM solutions at 40nm and beyond, SoC designers are forced to seek off-chip solutions. An off-chip solution, of course, has its disadvantages. Adding a chip adds to the BOM, increases pin counts and form factor, and limits the speed of execution.
With the announcement of Itera, the new NVM intellectual property (IP) block from Kilopass, this is all changing. Itera is an MTP solution implemented in standard logic CMOS and scalable to 20nm and beyond. Other advantages include 24X faster performance over traditional Serial Peripheral Interface (SPI) E2PROM and Flash and up to 70% cost savings over external solutions. Itera is already qualified at the 40nm process node, with test chips currently being characterized at 28nm HKMG.
This paper first considers challenges facing existing MTP NVM technologies. Next, it describes key markets that would benefit from having on-chip MTP. The paper then presents the Kilopass Itera MTP NVM IP solution.
Challenges facing existing MTP NVM technologies
The mainstay of the on-chip MTP NVM market is dominated by the Flash and EEPROM technologies, both of which are based on the concept of a floating gate, as illustrated in Figure 1.
In its un-programmed state, the floating gate has no effect and the standard gate can be used to turn the transistor on and off as for a standard MOS transistor. However, electrons coerced into the floating gate will block the action of the standard gate. This stored charge determines that the transistor has been programmed to contain a logic 1 value.
The advantage of Flash and EEPROM memories is that the floating gate can be cleared and reprogrammed over and over again. However, the price to pay is the added processing steps required to augment standard CMOS technology: anywhere from 4 to 20 steps may be required. Thus, due to the complexity of fabrication, chips using on-chip Flash and EEPROM have trailed the state-of-the-art by one or two process nodes.
Even worse, it is difficult to scale these technologies to the latest process nodes. As the floating gate and oxide layers become thinner, leakage renders these technologies unreliable for long-term data retention. Even at relatively mature nodes like 90nm, if a chip containing this class of memory is heated—as can happen when a cell phone is left in a car in a hot climate—the electrons in the floating gate can acquire enough thermal energy to become mobile, bits start to lose charge, and the memory "forgets”.
There are a number of esoteric MTP NVM technologies, including FRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and PCM (Phase Change Memory). However, these are currently relegated to niche markets.
Who Needs Embedded MTP NVM?
As mentioned earlier, in recent years, three high-volume consumer markets: flat panel TV, PC, and mobile, have seen exponential growth. The next generation of TV is becoming a multi-function display. Tablets are transforming the PC ecosystem. Smartphones’ growing market acceptance is making the mobile handset ever more rich with features like mobile wallet.
As advertisers vie for consumers’ mindshare through these three end products, chipmakers are busy developing next generation products including RF transceivers, image sensors, multimedia processors, baseband processors, and applications processors. Increasing numbers of these ICs are manufactured in the 40nm node and beyond due to the need for more transistors to satisfy the ever-increasing complexity of functions coupled with the requirements for smaller form factor, power consumption, and cost. Co-incidentally, this is where there are no viable embedded MTP NVM solutions, and designers are forced to turn to the more expensive and less performance-effective external EEPROM and flash solutions.
Until now, that is. Kilopass Technology has answered this dilemma with its new Itera MTP NVM IP.
Introducing Itera MTP NVM technology
Itera is the industry’s first logic CMOS embedded MTP NVM IP offering in 40nm that delivers up to 1,024 cycles of programming capability. This provides more than enough programming cycles to satisfy the needs of over 50% of mobile and consumer applications: time stamp, security key revocation, firmware updates, and trimming adjustments, etc.
Like other Kilopass products, Itera is built on Kilopass’ patented 2T OTP memory cell. How can OTP be multiple time programmable? At first glance, this appears to be illogical, but it is interesting how the advancement of technology has made this possible and made the evolution of OTP to MTP a logical course. The theory is simple – the size of an individual transistor has scaled down so much over generations of process nodes that an amazing number of transistors can be packed into the same area. (Moore’s Law: the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years, i.e., every process node.)
As Itera is built on Kilopass’ patented two standard CMOS transistor (2T) bit-cell technology, it takes full advantage of this Law: from 180nm to 20nm, the density of memory increased by 25 times! As a result, cost-competitive on-chip NVM can be built using the 2T technology. The Itera block consists of a memory array and analog and digital circuits including high voltage switches, charge pump, bandgap, controller, etc. Given that the 2T bit-cell cost is practically free, the memory array can be over-provisioned and partitioned in into sub-arrays. Consider the depiction illustrated in Figure 2. When the device is programmed for the first time, the controller will write to the first sub-array as illustrated in Figure 2(a). When the device is subsequently “erased” and reprogrammed, the controller will write to the second sub-array as illustrated in Figure 2(b). Similarly, the next time the device is reprogrammed, the controller will write to the third sub-array as illustrated in Figure 2(c).
Itera may be partitioned into anywhere from 100 to 1,024 sub-arrays, which means it can undergo anywhere from 100 to 1,024 programming cycles.
Example applications
An endurance of 1,024 cycles may not seem like much when compared with the 10K endurance offered by floating gate technology. But a second look at this number reveals it is not bad at all; in fact, it is more than sufficient for many applications. Instead of asking how many cycles of endurance are available, perhaps the more appropriate question to ask is: “How many cycles of endurance are actually required?”
For example, consider a small embedded device that requires 64Kbits of boot code. Even if the worst programmer in the world wrote this boot code, it is almost inconceivable that anyone would ever need to upgrade the code more than 1,024 times.
As shown in Table 1, the endurance number Itera offers makes it suitable for a variety of tasks, such as patchable program storage (e.g. microcode updates), time stamps (when was the oil last changed?), trimming and calibration (adjusting original settings to compensate for degradation due to aging or changes in the operating environment), security keys (revocation of access). For those applications that require less than 1,024 cycles of endurance, Itera offers a very cost effective solution.
Eventually, in five to ten years, on-chip floating gate technology will migrate to 40nm and beyond. But even then, the endurance will not be 10K, but one or two orders less, similar to what Itera can offer today.
eXecute-In-Place (XIP)
Speed in execution is another difference between external serial flash device and embedded NVM. Consider the problems associated with such a scenario of executing code as illustrated in Figure 3(a).
Due to the relatively slow speed of the SPI, it is very common for the code stored in the Flash to be first copied into on-chip SRAM, from where it is ultimately executed.
By comparison, an on-chip Itera block, as illustrated in Figure 3(b), can be accessed 24 times faster than an external SPI Flash device; 4 times faster than a Quad SPI interface. Thus Itera supports the high data rates required for XIP code storage. With XIP, programs are directly executed from memory that stores the code. This eliminates the need for shadow SRAM, reduces costs, and increases overall system performance.
Cost benefits
An example implementation is illustrated in Figure 4: a product requiring access to 64Kb of MTP NVM memory and a production volume of 10M chips per year with an average cost of $3,500 per wafer (40nm) over three years of the product’s life. In the case of the external EEPROM option, there will be direct costs of ~$0.29 per chip plus ~$0.05 in system overhead resulting in an additional ~$0.34 per product in BOM costs. By comparison, replacing the external EEPROM with on-chip Itera would result in higher performance, lower power consumption, and a smaller and lighter board, along with savings of $6.3M per product life ($10.2M versus $3.9M).
Ease of use
A key feature of Itera is the ease of integration with the rest of the design. Itera comes with an Open Core Protocol v3.0 interface. As many SoCs already employ OCP to integrate IP blocks from multiple sources (at the time of this writing, more than half a billion chips have shipped with the OCP inside), it means that designers do not need to learn a new or proprietary interface when it comes to deploying blocks of Itera in their devices.
The OCP International Partnership Association (OCP-IP) is an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol. In turn, the OCP is the first fully supported, openly licensed, comprehensive interface socket for semiconductor intellectual property (IP) cores.
Summary
The vast majority of today’s high-volume chip designs in 40nm processes and below requires some form of non-volatile memory (NVM). If at all possible, an embedded solution is preferred, because it will increase security, reduce the bill of materials (BOM), shrink board real estate, reduce power consumption, increase performance, enable faster wake up time, minimize costs, reduce time-to-market (TTM), and increase reliability.
In many cases the use of one-time programmable (OTP) memory will suffice, but there are high-value applications that need embedded MTP to provide the ability to be updated. Two very common forms of embedded MTP NVM, EEPROM and Flash, however, are not available at the 65nm process node and below, forcing designers to seek more expensive and less performance-effective off chip solutions.
Itera from Kilopass fills this void. With endurance up to 1,024 programming cycles, qualified at the 40nm process node (scalable down to 20nm and beyond), clear savings of over 70%, and 24X faster performance over external serial Flash, Itera is the best choice for embedded MTP NVM in SoC designs.
About the author
David Hsu is Senior Field Marketing and Applications Manager at Kilopass Technology Inc. He graduated from The Ohio State University and received his Master’s degree in EE from Purdue University.
David started his career in Siemens Components in the telecommunication division; later at Datapath Systems’ read channel program and as principal engineer at LSI Logic HyperPHy SerDes group from1998 to 2006. Between 2006-2009, David worked at TSMC in the role of customer support and in IP/Library quality management.
In many applications one-time programmable (OTP) memory is used, but there are other high-value applications requiring multi-time programmable (MTP) memory that can provide the ability for the device to be updated. For example, due to degradation from aging or changes in their operating environment, it may become necessary to re-calibrate and re-trim mixed signal circuits like high-performance DACs that are integrated in today’s complex SoCs. Other examples include access key revocation, upgrading to a new revision of code, and periodic data logging.
Two very common forms of MTP NVM are EEPROM and Flash, both of which are based on the concept of a floating gate. These technologies in the embedded form are available only in higher process nodes such as 180nm, 130nm, and 90nm, but they are not available at more advanced nodes. This is due to the fact that, as the floating gate and oxide layers become thinner, leakage issues render these technologies unreliable for long-term data retention. Consequently, with no embedded MTP NVM solutions at 40nm and beyond, SoC designers are forced to seek off-chip solutions. An off-chip solution, of course, has its disadvantages. Adding a chip adds to the BOM, increases pin counts and form factor, and limits the speed of execution.
With the announcement of Itera, the new NVM intellectual property (IP) block from Kilopass, this is all changing. Itera is an MTP solution implemented in standard logic CMOS and scalable to 20nm and beyond. Other advantages include 24X faster performance over traditional Serial Peripheral Interface (SPI) E2PROM and Flash and up to 70% cost savings over external solutions. Itera is already qualified at the 40nm process node, with test chips currently being characterized at 28nm HKMG.
This paper first considers challenges facing existing MTP NVM technologies. Next, it describes key markets that would benefit from having on-chip MTP. The paper then presents the Kilopass Itera MTP NVM IP solution.
Challenges facing existing MTP NVM technologies
The mainstay of the on-chip MTP NVM market is dominated by the Flash and EEPROM technologies, both of which are based on the concept of a floating gate, as illustrated in Figure 1.
Figure 1. Flash/EEPROM floating gate transistor.
In its un-programmed state, the floating gate has no effect and the standard gate can be used to turn the transistor on and off as for a standard MOS transistor. However, electrons coerced into the floating gate will block the action of the standard gate. This stored charge determines that the transistor has been programmed to contain a logic 1 value.
The advantage of Flash and EEPROM memories is that the floating gate can be cleared and reprogrammed over and over again. However, the price to pay is the added processing steps required to augment standard CMOS technology: anywhere from 4 to 20 steps may be required. Thus, due to the complexity of fabrication, chips using on-chip Flash and EEPROM have trailed the state-of-the-art by one or two process nodes.
Even worse, it is difficult to scale these technologies to the latest process nodes. As the floating gate and oxide layers become thinner, leakage renders these technologies unreliable for long-term data retention. Even at relatively mature nodes like 90nm, if a chip containing this class of memory is heated—as can happen when a cell phone is left in a car in a hot climate—the electrons in the floating gate can acquire enough thermal energy to become mobile, bits start to lose charge, and the memory "forgets”.
There are a number of esoteric MTP NVM technologies, including FRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and PCM (Phase Change Memory). However, these are currently relegated to niche markets.
Who Needs Embedded MTP NVM?
As mentioned earlier, in recent years, three high-volume consumer markets: flat panel TV, PC, and mobile, have seen exponential growth. The next generation of TV is becoming a multi-function display. Tablets are transforming the PC ecosystem. Smartphones’ growing market acceptance is making the mobile handset ever more rich with features like mobile wallet.
As advertisers vie for consumers’ mindshare through these three end products, chipmakers are busy developing next generation products including RF transceivers, image sensors, multimedia processors, baseband processors, and applications processors. Increasing numbers of these ICs are manufactured in the 40nm node and beyond due to the need for more transistors to satisfy the ever-increasing complexity of functions coupled with the requirements for smaller form factor, power consumption, and cost. Co-incidentally, this is where there are no viable embedded MTP NVM solutions, and designers are forced to turn to the more expensive and less performance-effective external EEPROM and flash solutions.
Until now, that is. Kilopass Technology has answered this dilemma with its new Itera MTP NVM IP.
Introducing Itera MTP NVM technology
Itera is the industry’s first logic CMOS embedded MTP NVM IP offering in 40nm that delivers up to 1,024 cycles of programming capability. This provides more than enough programming cycles to satisfy the needs of over 50% of mobile and consumer applications: time stamp, security key revocation, firmware updates, and trimming adjustments, etc.
Like other Kilopass products, Itera is built on Kilopass’ patented 2T OTP memory cell. How can OTP be multiple time programmable? At first glance, this appears to be illogical, but it is interesting how the advancement of technology has made this possible and made the evolution of OTP to MTP a logical course. The theory is simple – the size of an individual transistor has scaled down so much over generations of process nodes that an amazing number of transistors can be packed into the same area. (Moore’s Law: the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years, i.e., every process node.)
As Itera is built on Kilopass’ patented two standard CMOS transistor (2T) bit-cell technology, it takes full advantage of this Law: from 180nm to 20nm, the density of memory increased by 25 times! As a result, cost-competitive on-chip NVM can be built using the 2T technology. The Itera block consists of a memory array and analog and digital circuits including high voltage switches, charge pump, bandgap, controller, etc. Given that the 2T bit-cell cost is practically free, the memory array can be over-provisioned and partitioned in into sub-arrays. Consider the depiction illustrated in Figure 2. When the device is programmed for the first time, the controller will write to the first sub-array as illustrated in Figure 2(a). When the device is subsequently “erased” and reprogrammed, the controller will write to the second sub-array as illustrated in Figure 2(b). Similarly, the next time the device is reprogrammed, the controller will write to the third sub-array as illustrated in Figure 2(c).
Figure 2. A high-level depiction of the way in which Itera MTP NVM works.
Itera may be partitioned into anywhere from 100 to 1,024 sub-arrays, which means it can undergo anywhere from 100 to 1,024 programming cycles.
Example applications
An endurance of 1,024 cycles may not seem like much when compared with the 10K endurance offered by floating gate technology. But a second look at this number reveals it is not bad at all; in fact, it is more than sufficient for many applications. Instead of asking how many cycles of endurance are available, perhaps the more appropriate question to ask is: “How many cycles of endurance are actually required?”
For example, consider a small embedded device that requires 64Kbits of boot code. Even if the worst programmer in the world wrote this boot code, it is almost inconceivable that anyone would ever need to upgrade the code more than 1,024 times.
As shown in Table 1, the endurance number Itera offers makes it suitable for a variety of tasks, such as patchable program storage (e.g. microcode updates), time stamps (when was the oil last changed?), trimming and calibration (adjusting original settings to compensate for degradation due to aging or changes in the operating environment), security keys (revocation of access). For those applications that require less than 1,024 cycles of endurance, Itera offers a very cost effective solution.
Table 1. Some example Itera applications
Eventually, in five to ten years, on-chip floating gate technology will migrate to 40nm and beyond. But even then, the endurance will not be 10K, but one or two orders less, similar to what Itera can offer today.
eXecute-In-Place (XIP)
Speed in execution is another difference between external serial flash device and embedded NVM. Consider the problems associated with such a scenario of executing code as illustrated in Figure 3(a).
Figure 3. Itera supports eXecute-In-Place (XIP)
Due to the relatively slow speed of the SPI, it is very common for the code stored in the Flash to be first copied into on-chip SRAM, from where it is ultimately executed.
By comparison, an on-chip Itera block, as illustrated in Figure 3(b), can be accessed 24 times faster than an external SPI Flash device; 4 times faster than a Quad SPI interface. Thus Itera supports the high data rates required for XIP code storage. With XIP, programs are directly executed from memory that stores the code. This eliminates the need for shadow SRAM, reduces costs, and increases overall system performance.
Cost benefits
An example implementation is illustrated in Figure 4: a product requiring access to 64Kb of MTP NVM memory and a production volume of 10M chips per year with an average cost of $3,500 per wafer (40nm) over three years of the product’s life. In the case of the external EEPROM option, there will be direct costs of ~$0.29 per chip plus ~$0.05 in system overhead resulting in an additional ~$0.34 per product in BOM costs. By comparison, replacing the external EEPROM with on-chip Itera would result in higher performance, lower power consumption, and a smaller and lighter board, along with savings of $6.3M per product life ($10.2M versus $3.9M).
Figure 4. The measurable benefits of using Itera
Ease of use
A key feature of Itera is the ease of integration with the rest of the design. Itera comes with an Open Core Protocol v3.0 interface. As many SoCs already employ OCP to integrate IP blocks from multiple sources (at the time of this writing, more than half a billion chips have shipped with the OCP inside), it means that designers do not need to learn a new or proprietary interface when it comes to deploying blocks of Itera in their devices.
The OCP International Partnership Association (OCP-IP) is an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol. In turn, the OCP is the first fully supported, openly licensed, comprehensive interface socket for semiconductor intellectual property (IP) cores.
Summary
The vast majority of today’s high-volume chip designs in 40nm processes and below requires some form of non-volatile memory (NVM). If at all possible, an embedded solution is preferred, because it will increase security, reduce the bill of materials (BOM), shrink board real estate, reduce power consumption, increase performance, enable faster wake up time, minimize costs, reduce time-to-market (TTM), and increase reliability.
In many cases the use of one-time programmable (OTP) memory will suffice, but there are high-value applications that need embedded MTP to provide the ability to be updated. Two very common forms of embedded MTP NVM, EEPROM and Flash, however, are not available at the 65nm process node and below, forcing designers to seek more expensive and less performance-effective off chip solutions.
Itera from Kilopass fills this void. With endurance up to 1,024 programming cycles, qualified at the 40nm process node (scalable down to 20nm and beyond), clear savings of over 70%, and 24X faster performance over external serial Flash, Itera is the best choice for embedded MTP NVM in SoC designs.
About the author
David Hsu is Senior Field Marketing and Applications Manager at Kilopass Technology Inc. He graduated from The Ohio State University and received his Master’s degree in EE from Purdue University.David started his career in Siemens Components in the telecommunication division; later at Datapath Systems’ read channel program and as principal engineer at LSI Logic HyperPHy SerDes group from1998 to 2006. Between 2006-2009, David worked at TSMC in the role of customer support and in IP/Library quality management.
|
|
|
|
|
Navigate to related information
