The Future of NOR flash memory

Usage Model
One usage model that has emerged is the storage of graphics data in NOR devices as a strategy to reduce or eliminate the need for a large SRAM or DRAM based graphics buffer.  In this scenario the host system is constantly pulling small amounts of data from a NOR device to “feed” a graphics controller.  The transfer size varies but a large portion of the transfers are on the order of 64-256B.  Figure 5 is a throughput comparison of a NOR and NAND based approach to this usage scenario.  The comparison assumes the following:

• 128B transfers
• 100ns NOR initial latency
• 25us SLC NAND initial latency
• 100MHz NOR bus rate (16b bus)
• 50MHz NAND bus rate (8b bus)
• NAND requires 1 additional read to perform a virtual to physical address translation

The 71x advantage that the NOR device has over NAND is largely due to the dramatically shorter initial latency (100ns vs. 25us).  NAND would not be an attractive choice for this usage scenario where the graphics data needs to reside directly in a low latency memory.  A NAND based solution would typically be implemented with the addition of a (DRAM) volatile memory  device where the relevant graphics data would be shadowed.  The low latency characteristics of the additional DRAM device would be able to achieve the throughputs required by this application.

 
FIGURE 5: Responsiveness NOR vs. NAND
NOR Flash completes 71 128B transfers while NAND completes its first.

Another emerging NOR usage scenario is the proliferation of low pin count SPI NOR Flash devices as the only non-volatile memory in the system.  These SPI devices are available with a four-bit data bus running at clock rates above 100MHz.  To further increase bus throughput some SPI NOR manufacturers have introduced DDR variants.  SPI NOR devices have historically been used in systems that shadow the NVM contents into SDRAM for code execution.  With the relatively high data rates and low latencies of SPI NOR Flash devices, host chipsets are able to perform code execution out of the SPI device.  This direct code execution out of a low cost serial memory is a trend that will continue to proliferate.

Conclusion
Engineers will gravitate toward the lowest cost solution as long as the targeted system level performance is attained.  The memory selection process is often complex because the preferred chipset does not support all possible volatile and non-volatile memory pairings.   Low and mid density NOR/PSRAM pairings will be attractive in many applications because of low pin count and low cost.  At higher densities, NOR Flash will continue to be attractive when low latency and high read throughputs are critical design criterion.

A continuing trend in NOR Flash evolution will be the balancing of pin count and bus read throughput.  SPI devices in particular have increased both operating frequencies and data bus throughput without increasing the signal count of the legacy interface.  SPI offerings are starting to appear that include a DDR bus protocol, significantly improving read performance.  SPI NOR and parallel NOR offerings are approaching inherent protocol constraints that will limit further increases in bus throughput.  Next generation NOR products will increasingly adopt the high speed interface strategies common in the DRAM world to continue improving read throughputs while keeping overall active signal count to a minimum.

In conclusion, NOR Flash will continue to offer performance and longevity advantages for the embedded landscape (from automotive, telnet, consumer to gaming to industrial applications) with low pin count interfaces, long product life cycles and superior read performance.