Design Article
PCM-NV progress report Part 3: A new direction using polyamorphic states
Ron Neale
5/13/2011 9:01 AM EDT
Filament or Bulk switching in SMs
The “S” shaped negative resistance I-V threshold switching characteristics are indicative of a the post threshold switching current having collapsed into a narrow filamentary path, a view with which Savransky [1] agrees [2] and suggests that in the ideal SM device the initial post-conducting filament would expand to include all the material contained in the necessary “pore” like structure.
In considering the operation of an SM, this will be of special importance if the material is initially deposited in the low threshold voltage state, as illustrated in Figure 5.
If in that state the SM device operates in a central filamentary region, then any attempt to switch the central region to the high threshold voltage state would leave the surrounding region in the low threshold voltage state, compromising the intended two terminal data state at the next read operation. No specific information was provided [1] on the threshold voltage characteristics of the PAC material in its virgin, as deposited, state. Savransky claims a threshold voltage range of a factor 3 is possible; if so, provided the as-deposited material is somewhere in that range the device will respond to a first attempt to write.
I raised the question of a first switching threshold voltage that might be different from subsequent switching events, the answer was that with modern processing techniques and clean contact interfaces there would be no “first firing” threshold voltage effect. At this time it is necessary to leave to others the verification of that claim and that completely stress-free chalcogenide glasses can be deposited. The actual state of the as deposited material is important because it raises the possibility that the first attempt to write an SM would always need to switch the device with a high threshold voltage pulse, just in case the as-deposited material had a threshold voltage with a value somewhere between the two intended threshold voltages and higher than the applied read voltage, a different type of first switching effect.
There are those who consider that the conducting filament is essentially at a constant temperature, for a fixed current. Its constant voltage characteristics are the result of a narrow annulus around the filament undergoing a small increase in temperature to become part of the filament and carry any increases in current. That is the lowest energy solution to accommodate increases in current when compared with the alternative of raising the temperature of the whole volume of the conducting filament. If this is the case, in order to raise the temperature of the filament to access the polyamorphic states, the filament will need to be constrained, or write pulses that exceed the filament response time (see Figure 4) will be required.
Another important aspect that will limit the possible maximum operating temperature of PAC-based SMs relates to the temperature coefficient of threshold voltage. Without need to resort to read design techniques that compensate for temperature changes, the operating temperature range cannot exceed the point where the high threshold voltage of a PAC-based SM equals the low threshold voltage. Specific quantitative information with respect to the way in which the threshold voltages of the two polymorphic states change with temperature and if they have the same temperature coefficient was not provided at this time by [1].
Thermal Stability of the polyamorphic states
If the transformation between polyamorphic states uses the post threshold switching power associated with crystallization in PCM devices, how stable will the devices be at elevated device operating temperatures? Claimed as the key to the possible success of NV memory devices based on PACs, is the energy of crystallization for a polyamorphic glass is high about 5 eV while that of the materials that are used for conventional phase change memory devices is low ~ 2.5eV. Furthermore the polyamorphic states have a potential energy of formation close to that of the amorphous-to-crystal transformations utilized in conventional PCMs. This suggests that the polyamorphic transformations occur at temperatures about 200 C.
Savransky used evidence from differential thermal analysis (DTA) to support the claim that it was possible to maintain PAC material at temperatures close to the PAC glass transition temperatures for extended periods of time without any evidence of crystallization. That is an absence of the exothermic peak in the DTA measurement normally associated with crystallization. In relation to memory device parameters what does that very condensed piece of solid state physics translate into? It is that access to the different polyamorphic states can be achieved with the level of power, current and temperature that is associated with the set (crystallization) process of the more conventional PCM and without the need of a reset pulse.
Figure 6 is a much-simplified conceptual interpretation of the movement between states with potential energy as a function of amorphous state. The two-polyamorphic data states of the SM are represented by deep potential wells, with the colored arrows showing the path between. Also shown is the relative height of the potential energy barriers that represent crystallization for PACs and for the material used for the more conventional PCM materials that require crystallization as one of the data states.
The thermal stability of the polyamorphic transitions one to the other will need to be tested in the context of devices in arrays operating at elevated temperatures.
Because the value of threshold voltage of an SM is the data state, any changes in its value will be a key aspect of stability. Glasses are super cooled liquids and as such will be subject to changes as a function of time and temperature. Savransky focused on rheological changes (glass flow) as the source of possible changes. This would appear to assume that the glasses are perfect after each switching event and do not suffer from any built in strain that might be annealed out and also effect a change in device threshold voltage characteristics. These possibly small changes are important considerations because the subtle polyamorph-to-polyamorph change reflects as a large change in threshold switching voltage, the cause and effect amplification factor is large.
At the device level and for PAC SM devices capable of operating at 125 OC, there are two memory options. It is claimed materials with glass transition temperatures of 210 OC will be suitable for NV memory device applications with data retention time of 10 years. While PACs with glass transition temperatures of 150 OC will be useful for DRAM applications requiring refresh at 1000 sec intervals.
Write-erase characteristics of SMs
In the more conventional PCM reset current density and temperatures of greater than 600 C appear to be the underlying cause of write/erase lifetime decreasing with scaling [3]. Given that is the case, PAC-based SMs will surely win on both counts. They will have no need for high current density reset pulses and the high temperatures required for melting conventional PCM during reset.
To make the write/erase lifetime case for PAC-based SMs, Savransky provides an example of chalcogenide-based threshold switch relay that operated for a verified 10E7 cycles, and he also cited unverified anecdotal evidence of threshold switches operating for 10E13 w/e cycles. My comment with respect to any long lifetime claims for threshold switches is always, why are there no examples of free running threshold switch oscillators using the negative resistance of switching? Intuitively, a write process that involves only bond movement (SMs), is likely to be faster than a crystallization process that involves the relocation and movement of atoms (PCM). For an SM, the switching time to move from one threshold voltage state to the other [1] claimed values of less than 5ns for a 100nm device. It was claimed with scaling a write time range of from 1 to 5ns would be achievable.
Scaling of SMs
I think the case for PAC-based SM scaling is made at the start of the previous section, i.e. no high current density reset pulse and reduced maximum operating temperatures. The latter will extend the scaling to levels far below that of PCM, before any area/volume heat/loss heat generated problems become considerations.
Savransky makes the case for scaling in the absolute limit by comparing the minimum size crystal that can be detected as existing in an amorphous matrix as 3nm and the minimum dimension of a different amorphous phase that can be detected in an amorphous matrix as 2nm.
Conclusion
The case in Savransky's paper for the possibility of a new type of NV memory based on polyamorphous chalcogenide (PAC) transformations was well made. Not with outlandish claims, but with sufficient evidence that would appear to make these materials worthy of more detailed examination by those skilled in the art, including those presently bogged down with scaling and reset current related problems while trying to use crystal-to-amorphous transformations to make competitive PCM non-volatile memory array products to replace Flash memory.
While the use of arbitrary units in many examples by Savransky, rather than quantitative data, provided useful relative information, it did represent one shortcoming of the presentation. One reason for that may be related to the disclosure of proprietary information.
As always, it is clearly necessary for the work reported in [1] to be repeated and the results confirmed. In fact, Savransky is looking for partners and ended his presentation with his own PAC needs list that ran as follows: Evaluation of SM at nano-scale dimensions and in array form, Industrial development of SM technology, and Academic study of PACs and relaxation semiconductors.
References
[1] Polyamorphous Chalcogenides (PAC) for DRAM and fast NVM: Concept and Initial Experimental Results, Proc MRS 2011, by Semyon Savransky, the TRIZ experts.
[2] Private communication by R Neale with Semyon Savransky.
[3] EETimes PCM Progress Report Part 2. Ron Neale
The “S” shaped negative resistance I-V threshold switching characteristics are indicative of a the post threshold switching current having collapsed into a narrow filamentary path, a view with which Savransky [1] agrees [2] and suggests that in the ideal SM device the initial post-conducting filament would expand to include all the material contained in the necessary “pore” like structure.
In considering the operation of an SM, this will be of special importance if the material is initially deposited in the low threshold voltage state, as illustrated in Figure 5.
If in that state the SM device operates in a central filamentary region, then any attempt to switch the central region to the high threshold voltage state would leave the surrounding region in the low threshold voltage state, compromising the intended two terminal data state at the next read operation. No specific information was provided [1] on the threshold voltage characteristics of the PAC material in its virgin, as deposited, state. Savransky claims a threshold voltage range of a factor 3 is possible; if so, provided the as-deposited material is somewhere in that range the device will respond to a first attempt to write.
I raised the question of a first switching threshold voltage that might be different from subsequent switching events, the answer was that with modern processing techniques and clean contact interfaces there would be no “first firing” threshold voltage effect. At this time it is necessary to leave to others the verification of that claim and that completely stress-free chalcogenide glasses can be deposited. The actual state of the as deposited material is important because it raises the possibility that the first attempt to write an SM would always need to switch the device with a high threshold voltage pulse, just in case the as-deposited material had a threshold voltage with a value somewhere between the two intended threshold voltages and higher than the applied read voltage, a different type of first switching effect.
There are those who consider that the conducting filament is essentially at a constant temperature, for a fixed current. Its constant voltage characteristics are the result of a narrow annulus around the filament undergoing a small increase in temperature to become part of the filament and carry any increases in current. That is the lowest energy solution to accommodate increases in current when compared with the alternative of raising the temperature of the whole volume of the conducting filament. If this is the case, in order to raise the temperature of the filament to access the polyamorphic states, the filament will need to be constrained, or write pulses that exceed the filament response time (see Figure 4) will be required.
Another important aspect that will limit the possible maximum operating temperature of PAC-based SMs relates to the temperature coefficient of threshold voltage. Without need to resort to read design techniques that compensate for temperature changes, the operating temperature range cannot exceed the point where the high threshold voltage of a PAC-based SM equals the low threshold voltage. Specific quantitative information with respect to the way in which the threshold voltages of the two polymorphic states change with temperature and if they have the same temperature coefficient was not provided at this time by [1].
Thermal Stability of the polyamorphic states
If the transformation between polyamorphic states uses the post threshold switching power associated with crystallization in PCM devices, how stable will the devices be at elevated device operating temperatures? Claimed as the key to the possible success of NV memory devices based on PACs, is the energy of crystallization for a polyamorphic glass is high about 5 eV while that of the materials that are used for conventional phase change memory devices is low ~ 2.5eV. Furthermore the polyamorphic states have a potential energy of formation close to that of the amorphous-to-crystal transformations utilized in conventional PCMs. This suggests that the polyamorphic transformations occur at temperatures about 200 C.
Savransky used evidence from differential thermal analysis (DTA) to support the claim that it was possible to maintain PAC material at temperatures close to the PAC glass transition temperatures for extended periods of time without any evidence of crystallization. That is an absence of the exothermic peak in the DTA measurement normally associated with crystallization. In relation to memory device parameters what does that very condensed piece of solid state physics translate into? It is that access to the different polyamorphic states can be achieved with the level of power, current and temperature that is associated with the set (crystallization) process of the more conventional PCM and without the need of a reset pulse.
Figure 6 is a much-simplified conceptual interpretation of the movement between states with potential energy as a function of amorphous state. The two-polyamorphic data states of the SM are represented by deep potential wells, with the colored arrows showing the path between. Also shown is the relative height of the potential energy barriers that represent crystallization for PACs and for the material used for the more conventional PCM materials that require crystallization as one of the data states.
The thermal stability of the polyamorphic transitions one to the other will need to be tested in the context of devices in arrays operating at elevated temperatures.
Because the value of threshold voltage of an SM is the data state, any changes in its value will be a key aspect of stability. Glasses are super cooled liquids and as such will be subject to changes as a function of time and temperature. Savransky focused on rheological changes (glass flow) as the source of possible changes. This would appear to assume that the glasses are perfect after each switching event and do not suffer from any built in strain that might be annealed out and also effect a change in device threshold voltage characteristics. These possibly small changes are important considerations because the subtle polyamorph-to-polyamorph change reflects as a large change in threshold switching voltage, the cause and effect amplification factor is large.
At the device level and for PAC SM devices capable of operating at 125 OC, there are two memory options. It is claimed materials with glass transition temperatures of 210 OC will be suitable for NV memory device applications with data retention time of 10 years. While PACs with glass transition temperatures of 150 OC will be useful for DRAM applications requiring refresh at 1000 sec intervals.
Write-erase characteristics of SMs
In the more conventional PCM reset current density and temperatures of greater than 600 C appear to be the underlying cause of write/erase lifetime decreasing with scaling [3]. Given that is the case, PAC-based SMs will surely win on both counts. They will have no need for high current density reset pulses and the high temperatures required for melting conventional PCM during reset.
To make the write/erase lifetime case for PAC-based SMs, Savransky provides an example of chalcogenide-based threshold switch relay that operated for a verified 10E7 cycles, and he also cited unverified anecdotal evidence of threshold switches operating for 10E13 w/e cycles. My comment with respect to any long lifetime claims for threshold switches is always, why are there no examples of free running threshold switch oscillators using the negative resistance of switching? Intuitively, a write process that involves only bond movement (SMs), is likely to be faster than a crystallization process that involves the relocation and movement of atoms (PCM). For an SM, the switching time to move from one threshold voltage state to the other [1] claimed values of less than 5ns for a 100nm device. It was claimed with scaling a write time range of from 1 to 5ns would be achievable.
Scaling of SMs
I think the case for PAC-based SM scaling is made at the start of the previous section, i.e. no high current density reset pulse and reduced maximum operating temperatures. The latter will extend the scaling to levels far below that of PCM, before any area/volume heat/loss heat generated problems become considerations.
Savransky makes the case for scaling in the absolute limit by comparing the minimum size crystal that can be detected as existing in an amorphous matrix as 3nm and the minimum dimension of a different amorphous phase that can be detected in an amorphous matrix as 2nm.
Conclusion
The case in Savransky's paper for the possibility of a new type of NV memory based on polyamorphous chalcogenide (PAC) transformations was well made. Not with outlandish claims, but with sufficient evidence that would appear to make these materials worthy of more detailed examination by those skilled in the art, including those presently bogged down with scaling and reset current related problems while trying to use crystal-to-amorphous transformations to make competitive PCM non-volatile memory array products to replace Flash memory.
While the use of arbitrary units in many examples by Savransky, rather than quantitative data, provided useful relative information, it did represent one shortcoming of the presentation. One reason for that may be related to the disclosure of proprietary information.
As always, it is clearly necessary for the work reported in [1] to be repeated and the results confirmed. In fact, Savransky is looking for partners and ended his presentation with his own PAC needs list that ran as follows: Evaluation of SM at nano-scale dimensions and in array form, Industrial development of SM technology, and Academic study of PACs and relaxation semiconductors.
References
[1] Polyamorphous Chalcogenides (PAC) for DRAM and fast NVM: Concept and Initial Experimental Results, Proc MRS 2011, by Semyon Savransky, the TRIZ experts.
[2] Private communication by R Neale with Semyon Savransky.
[3] EETimes PCM Progress Report Part 2. Ron Neale
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janine.love
5/13/2011 9:19 AM EDT
We asked Ron Neale to select a paper from the Phase Change Memory session of the recent MRS that he considered might be able to make a significant contribution to bringing PCM to a position where competitive memory array products can be manufactured. Please make use of the comment section for questions or observations.
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resistion
5/13/2011 10:02 AM EDT
There is still the problem of threshold voltage drift in chalcogenide glasses. It would be more critical here.
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Volatile Memory
5/13/2011 1:01 PM EDT
Mr. Savransky appears to be a Charlatan of the caliber of Mr. Ovshinsky. His Soviet-propaganda book Engineering Of Creativity is a gem. The "use of arbitrary units" should have been your hint.
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R G.Neale
5/13/2011 6:01 PM EDT
Volatile Memory: I think I commented in my conclusion on the use of arbitrary units as a problem. Rather than personal attacks I think the first order of business must be for an independent third party to try and reproduce the results reported by Savransky.
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http://www.lulu.com/spotlight/poconoarmchairreview
5/14/2011 11:19 PM EDT
I personally would like to know what Harry Potter thinks of all this.
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R G.Neale
5/13/2011 5:50 PM EDT
Resiston: I agree threshold voltage drift, or post switching recovery, will be an important consideration for PAC based SMs.
If the post switching recovery in threshold switches is the same as in PCM memory devices after reset, then that may be an important clue to the conditions, especially temperature, that exist in the conducting filament of a threshold switch. Be it PAC based or any other type for that matter.
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resistion
5/14/2011 12:02 AM EDT
Since the thermal budget exceeding 200 c is common, it will be hard to fabricate these films in the desired initial states.
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resistion
5/14/2011 12:07 AM EDT
The situation of figure 1 also indicates a destructive read by applying the lower threshold voltage.
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Semyon Savransky
5/15/2011 6:24 PM EDT
Dear Ron,
Thank you for the review that really extends my MRS presentation.
Let me clarify some points:.
PCM as well as some of types of RRAM have low efficiency (only few percents) because of huge entropy penalties related with operation between ordered and disordered states, while switching memory SM supposes to be more total energy efficient and operates at lower currents.
Ge-Si-As-Te glass was used by Stanford Ovshinsky in stable threshold switches but to best of my knowledge it is NOT polyamorphic.
Although initial current filamentation occurs in SM devices they are NOT necessary should have pore structure, actually I used devices with structure similar to a planar capacitor. I not sure that PAC material must be deposited in the low threshold voltage state for nano-size SM devices but no studies have been performed. Initial values of threshold voltage were masked by imperfections of technology used to produce micro-size devices.
I observed a threshold voltage range of the factor slightly above2 only.
Because no detailed studies of PAC were conducted I do not have data about threshold voltage temperature coefficients.
When I made PCM presentation on behalf of Intel Corporation, managers always asked to use arbitrary units and mirror some relations to protect the company proprietary information and IP, so I learned the lesson and applied it to this MRS presentation.
Regards,
Semyon Savransky
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Semyon Savransky
5/15/2011 6:33 PM EDT
Dear “Resistor”
I agree that threshold voltage Vth drift is possible in switching memory (SM). There are few methods to deal with drift in phase-change memory (PCM) on the active alloy, cell structure, programming pulses and array periphery levels, some of these solutions are applicable to SM. I think one of the most attractive is opportunity to use SM as DRAM with long refreshment times (about 1000 sec) there drift would not be so important.
I disagree with your assumption about destructive read. I was able indeed read low Vth few times without destruction but more studies are needed to claim fully non-destructive read, investigate drift, recovery, temperature coefficients for Vth, etc…..
The PAC films fabrication is not more difficult than fabrication of films for PCM or for threshold switches for nano-devices that have been done by Intel, Samsung and other companies.
Regards,
Semyon Savransky
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resistion
5/15/2011 9:04 PM EDT
Semyon, thanks for your reply. I was only referring to Figure 1. I accept that it would not be an issue in other cases where the current does not jump so high after exceeding Vth.
I couldn't get to attend MRS so I couldn't get to ask you other questions, such as the Tg range and also the crystallization temperature range.
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Semyon Savransky
5/17/2011 9:43 AM EDT
"Resistor",
Tg range is 140-270 deg. C, it can be expanded but
lower Tg glasses are not very technological and higher Tg will probably not be power efficient.
I did not observed crystallization in PAC in calorimetry and long-term storage. Based on calorimeter min heating speed estimate for crystallization energy is above 5 eV.
Regards,
Semyon Savransky
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