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Design Article

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Sator

6/14/2011 10:36 AM EDT

The statement "Any useable system will need to have the outputs terminated" is ...

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PeterMiller

6/3/2011 3:38 PM EDT

Case 2) Calculating the additional VDD supply to power the I/O function, which ...

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# Powering DDR memory and SSTL logic

## 5/24/2011 11:42 AM EDT

VTT
While VDDQ and VTTREF are relatively straightforward power supplies, the tracking termination voltage, VTT, is very different.  Most power converters are intended to source current to their output in order to maintain a regulated voltage or current at their output.  This is even true of a termination voltage for conventional logic, which is equal to the logic’s I/O voltage.

The mid-rail VTT termination voltage used in SSTL logic and DDR memory devices is different.  When the SSTL logic circuit generates a 0, an active pull-down device sinks current from the termination rail and the termination supply acts like a conventional supply voltage, sourcing the required current to maintain the desired termination voltage.  However, when the logic circuit generates a 1, a pull-up device sources current into the termination rail and the termination supply must suddenly become a load, sinking current sourced by the memory output.  This sink and source requirement increases the complexity of the VTT design significantly.

While this sink and source requirement complicates the memory design, it does provide a very valuable feature to the memory device.  Each logic “1” is sourcing current into the termination and each logic “0” is sinking a similar current out of the termination; therefore, the termination supply needs only to support the differential current (0’s - 1’s), normalizing the load currents and improving signal integrity over rail terminated logic.

Further increasing its complexity is the fact that it must track VTTREF very closely.  SSTL logic voltages are so low, that small variations between VTTREF and VTT could quickly erode the noise margin and degrade signal integrity.  Unlike a conventional regulator, with an output voltage set by comparing a divided version of the output voltage to a high-precision reference voltage, VTT solutions must compare an output voltage to the VTTREF voltage to ensure the widest possible noise margin, largest eye windows and most accurate data transfer.  This “tracking” requirement dramatically reduces the range of available devices.

VTT experiences more sever transients than most power supplies designed to support similar current.  VDQQ might transition from 10 percent to 90 percent nominal load in a few micro-seconds; however if the data and address lines of a DDR memory device switch from all ”0’s” to all ”1’s” the load seen by the termination supply rapidly changes from sourcing its maximum load, to sinking its maximum load.  This 200 percent load step makes transient performance critical for DDR memory power.

For simplicity and load balancing, VTT is generally generated using a tracking sink-source linear device, such as a high current op amp or dedicated sink-source low dropout regulator.  In such applications, VTT is commonly generated from VDDQ.  In addition to minimizing the power loss in a linear device by providing a low source voltage, this has the effect of normalizing the load current on VDDQ. The reason for this effect is that any address line not drawing current from the I/O function of VDDQ by generating a ”1” is sinking current from VTT, which is drawing the same current from VDDQ.  While not the most efficient solution, it does provide a consistent load equal to ½ - 1x the VTT current (ITT) on the VDDQ supply.

In much larger systems that terminate hundreds of lines, such as the long recording arrays used in digitizing test equipment, or in extremely power sensitive systems, such as battery powered solutions that need to operate for extended periods without recharging, a tracking synchronous buck switcher (see Figure 2), such as the TPS40042 can be employed.

A synchronous buck converter can draw current from its output, returning the recovered energy to its input voltage much like a boost converter.  This sink/source capability along with the efficiency of a synchronous buck makes it an ideal choice for high current or high efficiency termination.

When using a tracking synchronous buck converter to realize the termination voltage, it is critical to keep in mind  the source voltage for the termination converter.  While it is often ideal to operate the VTT regulator from VDDQ like before, the low VDDQ voltages might make this impractical or the cascade effect of double conversion can sacrifice some efficiency benefits that can be realized with alternate schemes.

When VDDQ is not used as the source for an active, switcher-based termination regulator, the termination regulator should share a common source with the VDDQ regulator.  This ensures that when sinking current from logic “1’s”, the active switcher cannot source more energy into its supply than is being drawn by the VDDQ regulator. This eliminates the need for the VTT sourcing supply to also sink load current and prevents a dangerous over-voltage condition at the source of the VTT regulator.

janine.love

5/24/2011 1:34 PM EDT

Peter presented this paper at ESC this spring and I asked him to create a version for the Memory Designline. If you have any comments or questions please sound off below.

zeeglen

5/24/2011 2:01 PM EDT

Good article, but page 2 (VTT) is the same content as page 1.

janine.love

5/24/2011 2:23 PM EDT

OK, looks like I fixed it. If anything strange happens again to this, please comment and I'll fix. Thanks.

kinnar

5/26/2011 3:47 AM EDT

The article is very much focused towards the need of the supplies for DDR RAM. If some graphs are used then it will better explain the requirement and it can provide better comparison.
It seems that the development of power supplies and regulators for DDRs will also be an area of research like development of DDRs.

Dr DSP

5/26/2011 12:09 PM EDT

Thanx for posting this article. Too many times memory articles focus on the timing of the interface and not on the power issues. This is a very useful overview. Now we just need a good reference design to pull it all together. Anyone know of a good one?

PeterMiller

5/26/2011 1:19 PM EDT

Dr DSP,
The article is based on an Embedded Systems Conference - Silicon Valley 2011 presentation that I gave in May 2011. Since it was a conference paper, I tried to avoid marketing specific reference designs.
The basic design will vary depending on the power levels needs, and currently most reference designs focus on the mid-current levels of 3-10A of VDDQ current & 1-2A of VTT current used by mobile computing solutions. An example of such a solution can be seen in the datasheet for the TPS51116 DDR Power Regulator from Texas Instruments.

tonytone

5/26/2011 3:52 PM EDT

TI's Vtt solution is LDO based with 50% efficiency. Enpirion's EV1340 4A and EV1380 8A Vtt's are switching solutions with higher efficiencies and a better solution with great ripple.

PeterMiller

5/26/2011 4:08 PM EDT

Tony,

TI also offers switch based VTT solutions in both internal MOSFET and external FET configurations, one is even mentioned in the article. Switched solutions are not always "better" they are different. They offer a small improvement in power consumption at the expense of increased cost, size and component count. For most applications where RMS current on the VTT rail below 1A, switching solutions save very little power. At 1A using DDR2, the savings is a mere 400mW if the switcher is 100% efficient!

letmesee

5/31/2011 7:28 AM EDT

Thanks for the article. I have a doubt wrt to this statement. "Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations. We only consider half of the differential pair strobe lines since one is always low while the other is high."
At one point you say a 1 and 0 would cancel out each other and draw no current. but when it comes to DQS/DQSX you are still counting half the number. Aren't they always 10 pair and so one doesn't need to count that current ?

PeterMiller

6/3/2011 3:29 PM EDT

Let Me See,

There are 2 different cases for reviewing the output current needed.
To calculate the source/sink current at the termination voltage however, the differential pairs alawys cancel as one of the pair sources current into the termination node and the other sinks current from the termination node, generating a net zero-current.

However, to calculate the additional input current on the VDD supply, we need to consider that half of the differential pair strobe-lines will always source current into the termination while the other sinks that current. While these currents cancel from the termination node's point of view, they don't cancel from the I/O Supply.

PeterMiller

6/3/2011 3:31 PM EDT

Something went horribly wrong with the formatting in that post. I will try to correct and clarify in my next comment

PeterMiller

6/3/2011 3:33 PM EDT

Case 1) Calculated the necessary termination current: When calculating the termination current (current sourced or sunk by the termination supply) Each differential pair is self-canceling since one line of the pair will source current and the other line sink an equal current. Producing a net 0 current.

PeterMiller

6/3/2011 3:38 PM EDT

Case 2) Calculating the additional VDD supply to power the I/O function, which is "Iout = 0A" in the datasheet VDDQ current specification. When calculating the additional VDD supply current, one must consider one half of each of the differential pairs because one of the pairs is sourcing current from the I/O supply (VDD) into the termination node while the other is sinking the same current from the termination node to ground. The currents cancel with respect to the termination node (they form a matched resistor divider) but there is still current flowing from VDD to VTT and from VTT to GND through the drivers of the differential pair and that current still needs to be sourced from VDD, even if it doesn't need to be sourced from VTT.

Sator

6/14/2011 10:36 AM EDT

The statement "Any useable system will need to have the outputs terminated" is not true.
If you use a point-to-point memory interface with on board packages, short leads and controlled driving impedance's, parallel termination of data lines may be removed, saving considerable power and relaxing Vtt req's. The address/control bus will of course still need parallel termination for buses wider than one package.