Powering DDR memory and SSTL logic

How much power do I need?
It’s easy to figure out how much power is typically needed, even if it’s not clear after reading through a datasheet. Let’s use a Micron 256Mbyte MT47H64M4 as an example:

Twenty-four pages into the 128 page datasheet lies the IDD specifications for this memory IC, with the expected input current for each state of operation (see Figure 3).  While it is possible to analyze the full operational cycle of the memory device and consider the worst possible rolling 10μs average and design a power solution capable of delivering only that much current, it is typically advantageous to design a power solution capable of providing continuous current equal to the maximum expected from the memory device.


(Click figure to download larger PDF)

In this case, under “Operating bank interleave read current,” IDD is specified as 320mA, but there are two key test conditions to this value.  First, IOUT = 0mA and ODT is disabled.  That means this configuration assumes there is no load and all of the outputs are unterminated.  Any useable system will need to have the outputs terminated and VDDQ must be able to supply the full termination current when all outputs are “high;” therefore, the VDDQ regulator must be able to source this maximum IDD current plus the full VTT termination current.

Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations.  We only consider half of the differential pair strobe lines since one is always low while the other is high.  Each of these 20 terminations can drive an output voltage up to 1.8V (VDD) into a typical 50Ω termination resistor (on-die or discrete) to a 0.9V termination voltage for 0.9V / 50Ω = 18mA for another 360mA of current.

This single 256Mbyte DDR2 memory chip might require as much as 680mA of 1.8V supply current to maintain its I/O, Logic and core operations.

For termination current on the VTT supply, it is also necessary to terminate address , bank address, clock, chip enable, and other memory logic lines for a total of 38 terminations and 684mA of termination current. Differential pairs can be ignored since the termination current sourced by one will automatically sink into the other (see Figure 4).


(Click figure to download larger PDF)

Finally, the VTTREF leakage current, when VTTREF is at a valid level (1/2 VDDQ) it is always less than 2μA.  If planning to use a simple resistor divider, it is important to note that 2μA of current across just 9kΩ of resistance introduces 18mV of error, the total allowable error in the programming of VTTREF, so relatively low resistor values should be used.

Power requirements become more complex as additional memory ICs are added.  Will the system allow multiple memory ICs to operate in this highest power interleaved read state or will only one device operate in this state at a time?  

Typically, only one memory device sharing common address and data lines will be in this active state at a time.  All other shared devices will be in a lower power state, such as a burst-refresh.  After reviewing the worst case operational state of each shared memory device, add up the IDD currents for these states for all of the memory devices.

For example, a 1GByte memory system might use four of these 256MByte ICs sharing the same address and data lines, with added logic to select which of the four memory devices is being accessed, effectively increasing the available address lines by two.  After reviewing the operational states, the designer determines that one device will be effective in continuous interleaved read, drawing 320mA of current, but the other three devices will be maintained in burst-refresh, drawing 180mA each for a total of 860mA of IDD current.

Since all of the outputs will be shared on a common data bus, and only one device will be driving these lines, the same 20 output currents are needed for 360mA of additional VDD current for a total of 1.22A of current from the 1.8V supply.

When we flip to termination current, many of the termination lines can be shared, using common data, address and bank selection. Chips enable and command lines must be separate so that each chip can be accessed separately; therefore, four additional terminations are required for each chip, bringing the total terminations to 50, for 0.9A of total termination current.

With four chips, each able to sink 2μA of VTTREF current, even lower resistor divider values must be used.  Additionally, an active VTTREF buffer or separate divider for each memory IC might be desirable.

With attention to detail and care about the specific needs of each supply voltage, memory power can be transformed from a daunting design task, to a truly valuable addition to design by maximizing noise margin and improving accuracy.  By understanding the function of each supply voltage, designers can more confidently select the power solutions that best meet their overall design goals and balance between size, power, efficiency, performance and cost.

About the Author
Peter James Miller is an applications engineer at Texas Instruments where he supports technical applications for DC/DC controllers and evaluations board (EVM) design, and develops internal and external applications training for DC/DC controllers. Peter received his BSEE & MSEE from Worcester Polytechnic Institute (WPI), Worcester, Massachusetts. He can be reached at ti_petermiller@list.ti.com.