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Sator

6/14/2011 10:36 AM EDT

The statement "Any useable system will need to have the outputs terminated" is ...

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PeterMiller

6/3/2011 3:38 PM EDT

Case 2) Calculating the additional VDD supply to power the I/O function, which ...

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# Powering DDR memory and SSTL logic

## 5/24/2011 11:42 AM EDT

How much power do I need?
It’s easy to figure out how much power is typically needed, even if it’s not clear after reading through a datasheet. Let’s use a Micron 256Mbyte MT47H64M4 as an example:

Twenty-four pages into the 128 page datasheet lies the IDD specifications for this memory IC, with the expected input current for each state of operation (see Figure 3).  While it is possible to analyze the full operational cycle of the memory device and consider the worst possible rolling 10μs average and design a power solution capable of delivering only that much current, it is typically advantageous to design a power solution capable of providing continuous current equal to the maximum expected from the memory device.

In this case, under “Operating bank interleave read current,” IDD is specified as 320mA, but there are two key test conditions to this value.  First, IOUT = 0mA and ODT is disabled.  That means this configuration assumes there is no load and all of the outputs are unterminated.  Any useable system will need to have the outputs terminated and VDDQ must be able to supply the full termination current when all outputs are “high;” therefore, the VDDQ regulator must be able to source this maximum IDD current plus the full VTT termination current.

Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations.  We only consider half of the differential pair strobe lines since one is always low while the other is high.  Each of these 20 terminations can drive an output voltage up to 1.8V (VDD) into a typical 50Ω termination resistor (on-die or discrete) to a 0.9V termination voltage for 0.9V / 50Ω = 18mA for another 360mA of current.

This single 256Mbyte DDR2 memory chip might require as much as 680mA of 1.8V supply current to maintain its I/O, Logic and core operations.

For termination current on the VTT supply, it is also necessary to terminate address , bank address, clock, chip enable, and other memory logic lines for a total of 38 terminations and 684mA of termination current. Differential pairs can be ignored since the termination current sourced by one will automatically sink into the other (see Figure 4).

Finally, the VTTREF leakage current, when VTTREF is at a valid level (1/2 VDDQ) it is always less than 2μA.  If planning to use a simple resistor divider, it is important to note that 2μA of current across just 9kΩ of resistance introduces 18mV of error, the total allowable error in the programming of VTTREF, so relatively low resistor values should be used.

Power requirements become more complex as additional memory ICs are added.  Will the system allow multiple memory ICs to operate in this highest power interleaved read state or will only one device operate in this state at a time?

Typically, only one memory device sharing common address and data lines will be in this active state at a time.  All other shared devices will be in a lower power state, such as a burst-refresh.  After reviewing the worst case operational state of each shared memory device, add up the IDD currents for these states for all of the memory devices.

For example, a 1GByte memory system might use four of these 256MByte ICs sharing the same address and data lines, with added logic to select which of the four memory devices is being accessed, effectively increasing the available address lines by two.  After reviewing the operational states, the designer determines that one device will be effective in continuous interleaved read, drawing 320mA of current, but the other three devices will be maintained in burst-refresh, drawing 180mA each for a total of 860mA of IDD current.

Since all of the outputs will be shared on a common data bus, and only one device will be driving these lines, the same 20 output currents are needed for 360mA of additional VDD current for a total of 1.22A of current from the 1.8V supply.

When we flip to termination current, many of the termination lines can be shared, using common data, address and bank selection. Chips enable and command lines must be separate so that each chip can be accessed separately; therefore, four additional terminations are required for each chip, bringing the total terminations to 50, for 0.9A of total termination current.

With four chips, each able to sink 2μA of VTTREF current, even lower resistor divider values must be used.  Additionally, an active VTTREF buffer or separate divider for each memory IC might be desirable.

With attention to detail and care about the specific needs of each supply voltage, memory power can be transformed from a daunting design task, to a truly valuable addition to design by maximizing noise margin and improving accuracy.  By understanding the function of each supply voltage, designers can more confidently select the power solutions that best meet their overall design goals and balance between size, power, efficiency, performance and cost.

Peter James Miller is an applications engineer at Texas Instruments where he supports technical applications for DC/DC controllers and evaluations board (EVM) design, and develops internal and external applications training for DC/DC controllers. Peter received his BSEE & MSEE from Worcester Polytechnic Institute (WPI), Worcester, Massachusetts. He can be reached at ti_petermiller@list.ti.com.

janine.love

5/24/2011 1:34 PM EDT

Peter presented this paper at ESC this spring and I asked him to create a version for the Memory Designline. If you have any comments or questions please sound off below.

zeeglen

5/24/2011 2:01 PM EDT

Good article, but page 2 (VTT) is the same content as page 1.

janine.love

5/24/2011 2:23 PM EDT

OK, looks like I fixed it. If anything strange happens again to this, please comment and I'll fix. Thanks.

kinnar

5/26/2011 3:47 AM EDT

The article is very much focused towards the need of the supplies for DDR RAM. If some graphs are used then it will better explain the requirement and it can provide better comparison.
It seems that the development of power supplies and regulators for DDRs will also be an area of research like development of DDRs.

Dr DSP

5/26/2011 12:09 PM EDT

Thanx for posting this article. Too many times memory articles focus on the timing of the interface and not on the power issues. This is a very useful overview. Now we just need a good reference design to pull it all together. Anyone know of a good one?

PeterMiller

5/26/2011 1:19 PM EDT

Dr DSP,
The article is based on an Embedded Systems Conference - Silicon Valley 2011 presentation that I gave in May 2011. Since it was a conference paper, I tried to avoid marketing specific reference designs.
The basic design will vary depending on the power levels needs, and currently most reference designs focus on the mid-current levels of 3-10A of VDDQ current & 1-2A of VTT current used by mobile computing solutions. An example of such a solution can be seen in the datasheet for the TPS51116 DDR Power Regulator from Texas Instruments.

tonytone

5/26/2011 3:52 PM EDT

TI's Vtt solution is LDO based with 50% efficiency. Enpirion's EV1340 4A and EV1380 8A Vtt's are switching solutions with higher efficiencies and a better solution with great ripple.

PeterMiller

5/26/2011 4:08 PM EDT

Tony,

TI also offers switch based VTT solutions in both internal MOSFET and external FET configurations, one is even mentioned in the article. Switched solutions are not always "better" they are different. They offer a small improvement in power consumption at the expense of increased cost, size and component count. For most applications where RMS current on the VTT rail below 1A, switching solutions save very little power. At 1A using DDR2, the savings is a mere 400mW if the switcher is 100% efficient!

letmesee

5/31/2011 7:28 AM EDT

Thanks for the article. I have a doubt wrt to this statement. "Reviewing the pin assignments of this device, we identify 16 data lines and up to eight differential strobe lines (if used) for a maximum of 20 terminations. We only consider half of the differential pair strobe lines since one is always low while the other is high."
At one point you say a 1 and 0 would cancel out each other and draw no current. but when it comes to DQS/DQSX you are still counting half the number. Aren't they always 10 pair and so one doesn't need to count that current ?

PeterMiller

6/3/2011 3:29 PM EDT

Let Me See,

There are 2 different cases for reviewing the output current needed.
To calculate the source/sink current at the termination voltage however, the differential pairs alawys cancel as one of the pair sources current into the termination node and the other sinks current from the termination node, generating a net zero-current.

However, to calculate the additional input current on the VDD supply, we need to consider that half of the differential pair strobe-lines will always source current into the termination while the other sinks that current. While these currents cancel from the termination node's point of view, they don't cancel from the I/O Supply.

PeterMiller

6/3/2011 3:31 PM EDT

Something went horribly wrong with the formatting in that post. I will try to correct and clarify in my next comment

PeterMiller

6/3/2011 3:33 PM EDT

Case 1) Calculated the necessary termination current: When calculating the termination current (current sourced or sunk by the termination supply) Each differential pair is self-canceling since one line of the pair will source current and the other line sink an equal current. Producing a net 0 current.

PeterMiller

6/3/2011 3:38 PM EDT

Case 2) Calculating the additional VDD supply to power the I/O function, which is "Iout = 0A" in the datasheet VDDQ current specification. When calculating the additional VDD supply current, one must consider one half of each of the differential pairs because one of the pairs is sourcing current from the I/O supply (VDD) into the termination node while the other is sinking the same current from the termination node to ground. The currents cancel with respect to the termination node (they form a matched resistor divider) but there is still current flowing from VDD to VTT and from VTT to GND through the drivers of the differential pair and that current still needs to be sourced from VDD, even if it doesn't need to be sourced from VTT.

Sator

6/14/2011 10:36 AM EDT

The statement "Any useable system will need to have the outputs terminated" is not true.
If you use a point-to-point memory interface with on board packages, short leads and controlled driving impedance's, parallel termination of data lines may be removed, saving considerable power and relaxing Vtt req's. The address/control bus will of course still need parallel termination for buses wider than one package.

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