Passive array architecture
Although driving a single cell is straightforward, driving a full array of memory cells is somewhat more complex. Thinfilm memories rely on a passive array structure, which consists of two sets of perpendicular electrodes with the ferroelectric film sandwiched between them. Use of a passive array allows for very small cell size, i.e. 4f2, and requires no transistors at the cell level. Thus, memory fabrication can be separated from that of the drive electronics, and for large storage capacity the number of transistors grows less than linearly, as , where N is the storage capacity. In a passive array architecture, unaddressed cells will experience disturb fields during write operations. With the choice of proper materials and processing, however, and by applying the proper drive protocol during read and write, disturb fields can be held to acceptable levels.
To read, a voltage pulse is applied on an addressed WL while both the unaddressed WLs and the BLs are kept 0V (or a fixed low voltage), see figure 2. The charges from all the addressed cells are sensed on each BL and the data content is determined.
To write data, a “V/3-protocol” is employed to minimize the disturbs on the unaddressed cells. By definition, the bits to be written to 0s must get the opposite polarity pules compared to the read operation. Therefore Vd is applied to those BLs while the addressed WL is kept at 0V. Now, in order to minimise the disturbs on the unaddressed cells on the BLs with addressed cells to be written to 0s, 2Vd/3 is applied to the unaddressed WLs. Furthermore Vd/3 is applied to the BLs for which the addressed cells should be written to 1s to minimise the disturb on those BLs. The actual setting of the cells to the 1-state is done by the read pulse. During the write cycle the Vd/3 pulse felt by the 1-state cells is only a (necessary) disturb. The drive protocol described above is key to make working passive arrays.