Proving the required 1% accuracy represented the first part of the work reported by the Stanford group. As well as structural analysis and PCM device simulation, the main focus of the second part of the Stanford work was the actual synapse emulation. The innovation and key to success of the Stanford Synapse emulation is the method by which the recorded resistance value is linked to the relative positions in time of the single pre- and post-synaptic pulses.
The method used is both simple and elegant. It is achieved by first changing the single pre-synaptic pulse (spike) into a pulse train of set and reset pulses, with the reset pulses increasing in amplitude (to cause a decrease the PCM conductance), followed by set pulses that will decrease the value of conductance. The mid-point in time between the two pulse types now becomes application time of the pre-synaptic pulse (spike).
In the Stanford work, the actual spike pair synapse emulation was carried out with a sufficient number of pulses: 15 to obtain 15 data points. Here, in order to explain the principles, it is easier to use 5 pulses as illustrated in Figure 4.
The division of the pre-synaptic pulse into a train of reset and set pulses poses a “which came first, a chicken or egg” type problem. For the emulation to succeed, there needs to be a link between the two pulse trains that is both intriguing and, at first sight, unexpected. The link is the voltage amplitude of the post-synaptic pulse (Vpost). It is possible to obtain a value of Vpost for the emulation starting with either the set or rest pulses, and they may have a different value. Consider first the steps required to develop the reset part of the pulse train.
From a fixed starting value of conductance, Vdmin is defined as the voltage of a reset pulse that will result in a reduction of the value of the PCM conductance by10%, see Figure 4(a).
The amplitudes of the following pulses (four in this example) are selected to result in equal steps needed to obtain the required 50% decrease in conductance, each time from the same fixed starting conductance value. In the actual emulation  these values ranged from 25kOhms to 100Kohms, with a midpoint at about 50kOhms. The difference between Vdmax and Vdmin then serves to define the value of Vpost, the voltage of the post-synaptic pulse.
The next step is to define the set pulse train. The lowest value in the set pulse train is obtained using a fixed starting voltage with a value close to Vpost. With this voltage as a starting point, the form of the set pulse (width, number of sub-pulses and voltages) must be found that causes an increase of 10% in the conductance the voltage and this is defined as Vpmin. Then, the voltage levels of the steps for the pulses in this part of the pre-synaptic pulse train that will incrementally increase the conductance to 100% must also be determined.
The next step, shown in Figure 4(b), is to obtain the pre-synaptic pulses that will be used in the emulation. This is achieved by reducing the value of the reset and set pulses by an amount: (Vdmax –Vdmin) = Vpost. The authors in a separate communication advise this was about 0.5Volts for the emulation.
Each data point in the emulation is obtained by applying the pre-synaptic pulse train to one electrode of the PCM and strobing it with a negative going pulse equal to Vpost applied to the other electrode. Figure 4 (b) shows three examples, (i), (ii) and (iii), one for each of one of the possible relative positions of the pre and post-synaptic pulses in the emulation, (i.e. lag. equal and lead respectively). Figure 4(c) shows the resulting voltage that would appear across the PCM when the post-synaptic pulse is coincident with one of the pulses in the pre-synaptic pulse train. Figure 4(d) shows how the resulting percentage change in resistance is used to build the data points that form the emulated synapse characteristics.
As explained above, Vpmin is defined as the minimum voltage that causes a 10% increase in the conductance of a PCM from a fixed initial value. It might be considered surprising and intriguing that Vpost, derived from the reset pulses, is almost equal to Vpmin. This is not a fundamental link; it is a forced link. A value close to Vpost must define the starting point in developing the set pulses. If this were not the case, it would not be possible to use the same Vpost to strobe both the reset and set pulse trains There is a second condition: the max voltage value of the set pulse needed to produce a 100% increase in conductance (Vpmax) cannot exceed 2 x Vpost.
It is of course possible to work in the opposite direction from that described above and use the set pulses as a starting point, obtaining a value for Vpost close to Vpmin and then obtain a set of reset pulses in the opposite way to that described above. Some might consider that complexity of the set pulses, especially if multiple sub-pulses are used, might make that the more desirable starting point to define Vpost as a voltage just less than Vpmin. Then adjust the single reset pulses to find the desired (Vdmax – Vdmin) value.
Sharp-eyed readers will have surely noticed that even without the post-synaptic pulse, all the reset part of the pulse train exceeds Vpmin. Apparently this is not a problem, these pulses are 50ns wide and spaced 10us apart. They are not considered to have any ability to modify the set state and can be ignored. As stated for the emulation each point was obtained by returning the state of the device to a known value, this was achieved by a write-verify technique. Duygu Kuzum one of the authors  informed us that this initial value is maintained in the range 5 to 8% .
How good is this PCM based synapse emulator especially with respect to STDP? The simplest way is to consider an equation that is used in bio-science to quantify the data obtained from real synapse.
It is: Δw = Ae-Δt/τ
Where Aw is the percentage increase in synaptic weight (PCM set level) with respect to the initial value, Δt is the pre-post spike interval. While A and τ are free parameters obtained from curve fitting the real data, they are a scaling factor and a time constant. Using the PCM emulator and varying the pulse spacing, the Stanford team was able, by changing the pulse spacing in the emulation, to control the value of τ . Another feature of the real-world synapse is a saturation value in the weight (conductance) of the synapse. With emulation that involved up to 100 pulse (spike) pairs the Stanford team demonstrated similar saturation behavior. The conclusion is the PCM can be used to accurately emulate all aspects of synapse behavior.
From the PCM perspective in the first part of this work, the repeatable control of 100 steps of resistance without recourse to read verify is interesting. The ability to cycle up and down repeatedly through the 100 step of PCM resistance (and in any cycle at any given step have the same value of resistance) must surely teach something about the internal structure.
From the structural analysis , it appeared that, for reset, the device operated by varying the size of the dome that was completely returned to the amorphous state, a process likely to be repeatable. However, as the low resistance crystallites grow during set pulse will they be the same and have the same resistance and grain boundary contact resistance? If not, the result would be a less repeatable value of overall resistance? It would appear from the structural analysis in  that the region of the device characteristics chosen for the proof of the 100 resistance value capability (i.e 10k to 100K) the volume of the amorphous material involved is close the size of the crystallites.
My view is this could provide the answer to the repeatability of the 100-step results and be applicable for those pursuing multilevel PCMs. That is providing the crystallites are of the right average size so as not to be completely removed on reset, epitaxial grow-back will return the situation exactly as it was before reset with the same total resistance. I would translate this into my rule that says: multilevel repeatability requires the volume of amorphous material used never exceeds the half the crystallite volume.
The quality of the PCM-Synapse emulation was very high. However, it would have been interesting to hear about the effects of temperature on the state of the PCM-synapse and comparison of device-to-device variation. Perhaps the major issue is that the Stanford research acknowledges that the future for PCM-based synapse and its application relies on PCM scaling and the development of 3D stacked matrices. The Stanford research seemed very selective in the detail they offered as supporting evidence from cited references for the possibility of meeting their PCM scaling and reduction in power dissipation requirements.
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About the Author
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R.G. Neale is the former editor-in-chief of Electronic Engineering
. Also, he is the co-author of Nonvolatile and reprogrammable, the read-mostly memory is here
, by R.G.Neale, D.L.Nelson and Gordon E. Moore, Electronics, pp56-60, Sept. 28, 1970.
Previous Progress Reports:
 Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing
Duygu Kuzum et al,Stanford, NanoLetters 2011.
 A Multi-Level-Cell Bipolar-Selected Phase Change Memory, Ferdinando Bedeschi, et al Proc ISSCC 2008
 EETimes http://www.eetimes.com/electronics-news/4217373/IBM-multilevel-cell-PCM#55892