Excellent read bandwidth and low access latency has made NOR Flash the technology of choice for real-time code execution from non-volatile memory. Parallel NOR devices continue as the memory of choice for many applications, but low pin count serial devices are becoming increasingly attractive for many mobile and embedded systems. The availability of new NOR Flash memory based upon the serial peripheral interface (SPI) provides developers with performance approaching parallel NOR while greatly reducing the device pin count.
With the rising complexity of today’s mobile devices and embedded systems, developers must address the increasingly challenging task of designing efficient memory subsystems that maximize system performance. Specifically, these systems often have megabytes of program code stored in non-volatile memory. For systems where performance is essential, code can be moved from non-volatile memory to fast RAM to speed execution. For systems where device size and cost are key, program code can be executed directly from non-volatile memory using an approach known as Execute-in-Place (XiP).
With either approach, the memory subsystem has a significant impact on overall system performance and the user experience. In general, the greater the memory bus bandwidth, the better the overall user experience. High read bandwidth and low latency enables instructions to be copied or fetched more quickly. Several other factors are also important for developers to consider when choosing a non-volatile memory technology.Parallel NOR Flash
Parallel NOR Flash devices have existed for nearly 25 years, and the bus has evolved over time to provide increasing levels of performance. NOR devices are available that are compatible with one or more of the following three bus protocols:
SPI-DDR NOR Flash
- Async Mode: Each 16 bit (2 byte) read operation requires a unique array access for every read operation.
- Page Mode: A contiguous range of addresses (typically 32 bytes) is read from the array during a single access. The target word (2 bytes) is output during the initial access and then as long as subsequent accesses are within the 32 byte region, a shorter “intra-page” access time is possible (i.e., when only changing the low order address bits). Any access outside of the 32 byte page address range will incur the longer inter-page initial access time.
- Burst Mode: Like page mode, burst mode reads a contiguous range of addresses (typically 32 bytes) from the array during a single initial access. After the required initial access time has elapsed, data is clocked out in a predetermined manner. Burst mode requires a few additional pins (typically 3 pins) but the rate at which data can be clocked out provides a significantly higher throughput than either page mode or async mode.
Bus pin count imposes a critical design constraint for mobile and embedded applications. I/O pins are not free: each I/O pin adds manufacturing and PCB layout cost as well as adds to device size. Pin count has become one of the deciding factors when choosing between NOR-based non-volatile memory or NAND-based options.
Systems using NOR-based memory historically employ a parallel bus between the host SoC and an external memory device. Parallel memory bus architectures provide high read bandwidth and low latency but they come at the expense of higher pin count compared to serial bus architectures. Serial bus architectures keep pin count down but at the cost of lower bandwidth and greater latency. The challenge for developers has been that they either get high bandwidth or low pin count but not both.
Developers now have the option of using NOR Flash memory based on the Serial Peripheral Interface (SPI) to meet the needs of mobile and embedded applications. SPI is a flexible interface that balances pin count and bandwidth to maximize overall system performance at a lower cost. SPI is a well-established standard that has served the electronics industry for over 25 years. There is already a wide variety of chipsets and peripheral devices available that natively support SPI. The SPI standard has also been extremely stable over the years. While operating voltages have dropped and clock rates increased to improve bandwidth, the core command protocol has remained unchanged.
SPI continues to evolve to meet shifting market needs. To offer increased throughput and support for multi-input/output (MIO) functionality, the interface has been extended to include 2-bit IO and 4-bit IO configurations. To further improve throughput devices have recently been introduced that use a double data rate (DDR) protocol. The combination of all of these improvements – higher clock frequency, 4-bit I/O and now DDR – has resulted in SPI-DDR NOR. The initial SPI-DDR offerings use the legacy 3V operating voltages which will allow bus operating frequencies of 66MHz up to perhaps 100MHz. Future offerings will include the SPI-DDR functionality on 1.8V devices that are expected to achieve bus operating frequencies between 100MHz and 133MHz. With enhanced read bandwidth, lower access latency, and a compact 6-pin bus interface, SPI-DDR NOR provides an attractive alternative for low-cost mobile and embedded devices that have historically used parallel NOR due to higher performance.