Design Article
Improving performance using SPI-DDR NOR flash memory
Qamrul Hasan and Cliff Zitlaw, Spansion
9/2/2011 11:15 AM EDT
Executing Code from RAM
The impact of a memory subsystem on system performance depends a great deal upon how the memory is being used. Determining the optimal balance of bandwidth and pin count, requires an analysis of how of the various types of NOR – SPI-DDR NOR, parallel NOR (Async, Page or Burst) – perform under different operating conditions.
For applications where performance is critical, execution speed can be improved by copying program code from non-volatile memory into higher throughput RAM. The memory subsystem affects system performance both when initially copying program code from NOR Flash to RAM during boot-up and when paging new segments of code during run-time.
During boot-up, code shadowing performance is determined by the ability of the NOR memory bus to transfer large blocks of data continuously. The ability to sustain burst rates is the key factor here given that the amount of data transferred could be many megabytes.. Performance in this case determines how long the system will take to start up and directly impacts the user experience. Once the program begins executing, system performance can be impacted whenever a new block of program code needs to be loaded (i.e., the overall program is larger than the available RAM and must be loaded in blocks as each section of code is needed). Sustainable throughput is again important since the amount of memory to load could be a few megabytes.
For the continuous read operations required during boot up or for demand paging, memory is accessed a page at a time. Figure 2 shows the performance of various NOR Flash memories using a typical 4 KB page size. Because SPI-DDR NOR performs each page read with a single command, memory read time for multiple pages increases in a linear fashion, providing a consistent sustained rate.
As can be seen in Figure 2, SPI-DDR NOR and the higher performing burst NOR provide comparable performance for both system boot and demand paging for a given frequency, making SPI-DDR NOR an attractive choice because of its low pin count. Applications that copy program data to RAM using Asynchronous or Page NOR can achieve a significant improvement in both performance and pin count by migrating to SPI-DDR NOR.
The impact of a memory subsystem on system performance depends a great deal upon how the memory is being used. Determining the optimal balance of bandwidth and pin count, requires an analysis of how of the various types of NOR – SPI-DDR NOR, parallel NOR (Async, Page or Burst) – perform under different operating conditions.
For applications where performance is critical, execution speed can be improved by copying program code from non-volatile memory into higher throughput RAM. The memory subsystem affects system performance both when initially copying program code from NOR Flash to RAM during boot-up and when paging new segments of code during run-time.
During boot-up, code shadowing performance is determined by the ability of the NOR memory bus to transfer large blocks of data continuously. The ability to sustain burst rates is the key factor here given that the amount of data transferred could be many megabytes.. Performance in this case determines how long the system will take to start up and directly impacts the user experience. Once the program begins executing, system performance can be impacted whenever a new block of program code needs to be loaded (i.e., the overall program is larger than the available RAM and must be loaded in blocks as each section of code is needed). Sustainable throughput is again important since the amount of memory to load could be a few megabytes.
For the continuous read operations required during boot up or for demand paging, memory is accessed a page at a time. Figure 2 shows the performance of various NOR Flash memories using a typical 4 KB page size. Because SPI-DDR NOR performs each page read with a single command, memory read time for multiple pages increases in a linear fashion, providing a consistent sustained rate.
As can be seen in Figure 2, SPI-DDR NOR and the higher performing burst NOR provide comparable performance for both system boot and demand paging for a given frequency, making SPI-DDR NOR an attractive choice because of its low pin count. Applications that copy program data to RAM using Asynchronous or Page NOR can achieve a significant improvement in both performance and pin count by migrating to SPI-DDR NOR.
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