With 28nm high-K metal Gate (HKMG) semiconductor production ramping in 2012, system-on-chip (SoC) designers are presented with the silicon real estate and economic incentive to integrate more functionality on-chip. One function that continues to be challenging for on-chip integration is non-volatile memory (NVM) despite its many advantages. At smaller process geometries, especially 28nm HKMG, the challenges to integrating NVM such as flash, pseudo flash, and e-fuse are effectively addressed with an anti-fuse solution.Comparing Alternative Embedded NVM Solutions
Perhaps the most common form of NVM is erasable many-time-programmable (MTP) embedded flash. A second form of NVM is pseudo-flash that can provide one-time- or few-time programmable (OTP/FTP) storage. A third form that provides OTP is e-fuse (electrically programmable embedded fuse). It blows a metal or poly link to store a bit of data. A fourth form, also OTP, is anti-fuse, which when fabricated is blank and may be programmed to a 1 by using gate oxide breakdown to create a low resistance conductive path.
The benefit of integrating flash on chip comes at the price of the added steps required to merge flash onto the logic process. As a result an embedded flash process typically lags the current state-of-the-art logic process by three generations. Combined flash and logic processes are starting to be available at 90nm, whereas standard logic process is ramping production in 28nm. As a general rule, the logic-flash process combination adds a 30- to 40-percent cost premium to the wafer. Thus, using an embedded flash process makes sense if the integrated flash constitutes over 50 percent of the total die area.
A variation of MTP flash is few-time-programmable (FTP) and one-time-programmable pseudo flash that uses a floating gate to trap electrons. It has fewer processing steps to implement than flash but suffers similar scaling challenges. Like the merged process flash, it too is not readily available in advanced process technology nodes due to the higher oxide leakage of advanced process oxide.
Yet another OTP solution is e-fuse. E-fuse has the advantage of being implemented in a standard logic process. The foundry provides e-fuse to SoC designers at a nominal charge, a plus for the foundry since the chip must be redesigned to use the e-fuse of another foundry. For the large number of applications that require a small amount of NVM storage, 4kbit or less, e-fuse provides a good solution at 40nm and above. If the application requires higher capacity, the real estate cost of adding additional instances begins to rise. At 28nm HKMG, e-fuse is a less optimal solution, especially when metal is used for manufacturing the fuse link.
The Benefits of Anti-Fuse
Anti-fuse is the other form of OTP that provides NVM storage. Its advantage over flash and pseudo flash is that it is completely compatible with the standard logic process and easily scales with each new process generation. Anti-fuse technology has unique features that are ideally suited for high growth applications that require the use of smaller process geometries:
• built on a standard logic process and using an ASIC operational flow,
• tamper-resistant for secure data storage,
• a wide variety of storage capacity options, and
• extended operating temperature range essential for automotive or industrial applications
Figure 1. This cross section of a Kilopass 2T bitcell shows the uniqueness of the anti-fuse technology. To write data, an elevated voltage applied to the 2T cell causes a breakdown of the gate oxide shown in the green circle. The breakdown converts an open to a low-resistance path. The gate oxide breakdown is very difficult to detect with conventional reverse engineering methods and the technology, which requires no special processing, can scale with each new standard CMOS process generation. Standard Logic Process & ASIC Test Flow
Because anti-fuse is built on a standard logic process and ASIC operational flow it is available on the most advanced process node including 28nm HKMG. It easily scales with each new process generation. Silicon data for 28nm HKMG shows that existing anti-fuse bit cell can scale to 20nm and beyond. Using a standard ASIC test flow means there are no special erase or bake requirements during test. And availability of built-in self-test (BIST) and repair provides for highly enhanced field programming yield, where failure cost is much higher. High Level of Security
With the advent of smartphone and follow-me media, SoC designers need a secure embedded storage medium for containing encryption keys and other security information that ensure secure digital rights management. Anti-fuse technology is the best alternative for keeping this data safe. Tampering using passive techniques such as current profiling to determine the word pattern is unsuccessful with anti-fuse. This results because anti-fuse bitcell current for “0”s and “1”s are much smaller than the current required for sensing or to operate the peripheral circuits to read the memory.
Tampering using invasive techniques such as scanning electron microscope (SEM) passive voltage contrast likewise has difficulty isolating the anti-fuse bitcell within the crosspoint memory array. Furthermore, it is difficult using chemical etching or mechanical polishing to locate the anti-fuse oxide breakdown. Variety of Storage Capacity Options
Because of its area scalability, Anti-fuse technology provides a wide variety of storage capacity options from a few kilobits all the way to several megabits. For applications requiring over 4kbits of storage, the anti-fuse solution is ideal because it simply adds storage bitcells without the associated overhead of adding a complete module of bitcells and control. Typically a small capacity memory module is dominated by overhead. Newer generation of anti-fuse memory architectures are providing storage capacities upward of 4 megabits of storage, sufficient for storing processor boot code securely and with the added advantaged of faster access compared to external NVM code storage. Furthermore, in applications where the contents of memory change infrequently, the OTP memory can function as MTP by storing new data in over-provisioned memory cells. Extended Temperature Range
Finally, with a wide operating temperature range anti-fuse technology provides the rugged operating characteristics needed for designs going into industrial applications. Anti-fuse has an operating temperature range between -40C and 125C. The ability of anti-fuse to operate at these temperature extremes provides designers building consumer electronics device a robust NVM storage solution. Conclusion
The various commercially available embedded NVM technologies each have a set of applications that they serve well. At process geometries above 90nm, embedded flash provides high-density storage for applications with frequently changing data. Pseudo-flash OTP/MTP is appropriate at 90nm and above for apps that require a small to medium NVM with a limited write endurance. E-fuse is a cost-effective single foundry solution for applications that require a very small amount of OTP storage at process geometries above 40nm. For applications that require small to medium storage capacity but must scale below 90nm to the latest process geometry, anti-fuse OTP offers an optimum solution.
If you liked this article...
- Head to the Memory Designline homepage for the latest updates in memory and storage.
- Sign up for the Memory Designline Newsletter, 2X a month delivered to your mailbox with the latest highlights from the site.
-------------------------------------------About the Author:
Andre Hassan is Field Marketing and Applications Director at Kilopass. He is an industry veteran with over 20 years of semiconductors and systems experience. Hassan brings a broad business experience in marketing, sales and operations, as well as depth in multiple engineering disciplines. Prior to Kilopass, he held senior management and engineering positions at Sigmatel, Monolithic System, S3, Sun Microsystems and Digital Equipment.