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R G.Neale
eista-The reason why refractory metals or metal silicides and nitrides are used ...
rbtbob
Maybe IBM/Macronix should add a thin layer of permanently crystallized ...
PCM Progress Report No. 6: Afterthoughts
Ron Neale
2/13/2012 3:20 PM EST
In the lead up period to International Solid-State Circuits Conference 2012 (February 19-23; San Francisco, CA) and Samsung's scheduled presentation of an 8-Gb phase change memory (PCM), we asked Ron Neale to help set the scene and bring us up to date with some of the most recent PCM developments. In part one of this two-part article, he reviews structural and materials advances, focusing on both benefits and challenges.
There was a time industry experts expected phase change memory (PCM) to revolutionize the market. Over recent months, those claims and certainties have been replaced by words like “promising” for any reported advances, suggesting there are still many problems remaining. Overhanging all the individual and disparate pieces of PCM progress is the ominous shadow of flash memory rapidly taking over the applications and market space originally claimed for PCM. Samsung1 issued what must be considered a dire warning on the ability of PCM to scale beyond 20 nm based on thermal considerations alone, as we will discuss. The same paper also acknowledged that PCM is presently stuck at the 4xnm technology node, while flash memory products already exist at the 2x node. For PCM, the window of commercial opportunity may have passed.
In this report, I have highlighted and commented on individual, and in most cases impressive pieces of PCM-related work in the areas of lithography, array-isolating devices, thermal crosstalk, new PCM materials, and more. All would appear to still be a long way from incorporation into a single PCM array that is competitive in price, performance, and bit capacity with alternative memory solutions, though. Late last year at the 2011 IEEE International Electron Devices Meeting (IEDM11; December 5-7; Washington, DC), the PCM papers progressed toward solving different PCM performance and fabrication problems at the 2Xnm, 3Xnm, 4Xnm, and 5Xnm nodes. Much of the focus of attention by researchers is on engineering of the interface between the chalcogenide layer and the lower electrode to confine the active region and minimize the reset current, which requires an optimum combination of thermal and electrical design. The PCM cell bottom electrode has grown from the simple planar structure to a number of “promising” options (see figure 1). In just this one element of any potential PCM array, the complexity has increased dramatically and there is no certainty that these structures will scale to 2Xnm and below to produce useful PCM devices. The inverse relationship between complexity and yield or cost is starting to become a serious consideration for further attempts at PCM scaling.
Probing the 20-nm node
The approach of Samsung was to address the scaling problems of PCM at the 20-nm node with a 4F2 cell based on the “dash” structure (see figure 2).1 The notable features are the use of selective epitaxial growth (SEG) to create a high-aspect-ratio single-crystal matrix isolation diode. The engineering of the diode is impressive with a need to maintain the lowest value of forward voltage Von while at the same time reducing series parasitic resistance and maintaining a low value of W/L word line resistance without compromising the Ioff, the latter now a very important consideration in a large array. The dash cell structure is a confined PCM type, achieved by the creation of a concave upper surface for the bottom electrode. I raised with the authors1 the question as to the degree to which the tips of the curved surface of the lower electrode will create an initiating hot spot along the surface during the set operation or even tracking paths. The Samsung group considers that in normal operation, the upper electrode of crystallized germanium antimony tellurium (GST) is well removed, which allows them to avoid this problem. Clearly, variations in reset pulse amplitude will determine how much GST material is reset. The authors reported reset currents of 90 μA. This calculates into current density of 5.4 × 107 A/cm2 for both the memory cell and the diode.
There was a time industry experts expected phase change memory (PCM) to revolutionize the market. Over recent months, those claims and certainties have been replaced by words like “promising” for any reported advances, suggesting there are still many problems remaining. Overhanging all the individual and disparate pieces of PCM progress is the ominous shadow of flash memory rapidly taking over the applications and market space originally claimed for PCM. Samsung1 issued what must be considered a dire warning on the ability of PCM to scale beyond 20 nm based on thermal considerations alone, as we will discuss. The same paper also acknowledged that PCM is presently stuck at the 4xnm technology node, while flash memory products already exist at the 2x node. For PCM, the window of commercial opportunity may have passed.
In this report, I have highlighted and commented on individual, and in most cases impressive pieces of PCM-related work in the areas of lithography, array-isolating devices, thermal crosstalk, new PCM materials, and more. All would appear to still be a long way from incorporation into a single PCM array that is competitive in price, performance, and bit capacity with alternative memory solutions, though. Late last year at the 2011 IEEE International Electron Devices Meeting (IEDM11; December 5-7; Washington, DC), the PCM papers progressed toward solving different PCM performance and fabrication problems at the 2Xnm, 3Xnm, 4Xnm, and 5Xnm nodes. Much of the focus of attention by researchers is on engineering of the interface between the chalcogenide layer and the lower electrode to confine the active region and minimize the reset current, which requires an optimum combination of thermal and electrical design. The PCM cell bottom electrode has grown from the simple planar structure to a number of “promising” options (see figure 1). In just this one element of any potential PCM array, the complexity has increased dramatically and there is no certainty that these structures will scale to 2Xnm and below to produce useful PCM devices. The inverse relationship between complexity and yield or cost is starting to become a serious consideration for further attempts at PCM scaling.
Figure 1: Confining the active region, the growing complexity of the PCM electrode structure.
Probing the 20-nm node
The approach of Samsung was to address the scaling problems of PCM at the 20-nm node with a 4F2 cell based on the “dash” structure (see figure 2).1 The notable features are the use of selective epitaxial growth (SEG) to create a high-aspect-ratio single-crystal matrix isolation diode. The engineering of the diode is impressive with a need to maintain the lowest value of forward voltage Von while at the same time reducing series parasitic resistance and maintaining a low value of W/L word line resistance without compromising the Ioff, the latter now a very important consideration in a large array. The dash cell structure is a confined PCM type, achieved by the creation of a concave upper surface for the bottom electrode. I raised with the authors1 the question as to the degree to which the tips of the curved surface of the lower electrode will create an initiating hot spot along the surface during the set operation or even tracking paths. The Samsung group considers that in normal operation, the upper electrode of crystallized germanium antimony tellurium (GST) is well removed, which allows them to avoid this problem. Clearly, variations in reset pulse amplitude will determine how much GST material is reset. The authors reported reset currents of 90 μA. This calculates into current density of 5.4 × 107 A/cm2 for both the memory cell and the diode.
Figure 2: The Samsung selective epitaxial growth PCM cell with cup-shaped silicide confining BE (simplified).
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Volatile Memory
2/15/2012 11:56 AM EST
Mr. Neale: You should stop this charade. Ovonyx will file for Chapter 11 by the end of the year. Samsung, Micron, Intel, IBM, Hynix - everybody has abandoned this thing already. The phase-change memory scam is over.
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R G.Neale
2/15/2012 4:20 PM EST
NonVolatile Memory: It is not up to me to declare the end point for the PCM project. If you read back over the six PCM progress reports and my other articles in EETimes my position is clear. I certainly think the situation now looks very bleak and I tried to convey that message. It is my view, based on published work, that the problems of: Element separation, Current Density, Scaling,Thermal Cross talk, Growing Device Complexity and Yield all weigh heavily against a bright commercial future for PCM. That does not make me, by asking questions and reporting innovative pieces of work by those who believe they can solve the problems part of a charade, or for that matter them.
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Volatile Memory
2/15/2012 5:18 PM EST
Mr. Neale: Ok, then I am declaring it. Nobody believes that PCM's "problems" can be solved. All efforts to commercialize PCM in volume have repeatedly failed since 1970. Anybody who pretends that PCM has even a slight chance to succeed is either totally uninformed or intentionally disingenuous. In other words, PCM is a techno-Ponzi.
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resistion
2/15/2012 11:07 PM EST
It is questionable to use the poor conductor, as that will up your voltage budget. You also can't RESET as fast.
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R G.Neale
2/16/2012 5:32 AM EST
resistion-If you mean the poor conductor both electrical and thermal (TaN) in the IBM/Macronix PCM electrode design then they mitigate the downside by having it spread as a thin large diameter layer at the contact point “the base of the bucket” then the (TiN) is used as the low resistance electrical conductor. I think the problem with scaling this structure is the thermally insulating sidewall layer of TaN with a thickness of 7 to 8nm will have to be reduced just as the area/volume heat loss problem worsens. If not the minimum diameter device will be 16nm plus the diameter of any TiN that is carrying the reset current. What will be very interesting next week at ISSCC2012 is to see if Samsung stay with the concave dash structure for the 8G-bit or have moved to the bucket structure.
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eista
2/16/2012 11:06 AM EST
Nice analysis, Dr. Neale
Following the thought, is the thermal-electric material good for bottom electrode (good electrical conductivity and poor thermal conductivity), such as SiGe, BiTe?
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resistion
2/16/2012 11:52 AM EST
Normally, electrical and thermal conductivity go together, supported by the electrons.
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resistion
2/16/2012 11:46 AM EST
Despite the bucket arrangement, they still have the issues, the voltage and power consumption is higher from the added resistance, which is not completely bypassed.
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kinnar
2/16/2012 6:24 AM EST
Is this Golden Composition is realizable in a practical industrial environment?
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R G.Neale
2/16/2012 9:45 AM EST
Kinnar-IBM did report a comparison test that involved baking cells from a 128M-bit PCM array with their new Golden Composition for 6 hrs at 190 degrees C and similar cells using GST225 that demonstrated its superiority give or take a few tail-bits. The GST225 based devices failing the test at 160 C test. The IBM team was very conservative in their conclusion suggesting that their work should generate further interest in material engineering as a way forward for PCM. IBM did not state the number of write/erase cycles that the devices they tested had accrued. I was more concerned about the vulnerability of the Golden Composition to element separation, especially with scaling, and the possibility, using my fig 3, that element separation might push the GC into the valley in the crystallization temperature surface where lies GST225 and compromise the performance. The answer to your question regarding the ability to withstand a practical industrial environment will only be found when the Golden Composition is used to fabricate a useful size array or the IBM 128M-bit PCM arrays are subjected to that environment.
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rbtbob
2/16/2012 11:59 AM EST
Maybe IBM/Macronix should add a thin layer of permanently crystallized chalcogenide like what HP says develops in their memristor: "...in one-to-two nanometers thick region, the film cools in an annealing-like like process which leaves the film in a fixed crystalline state that should remain that way indefinitely...." It would even out both the heat and current transfer.
AND they should dope their Golden Composition with Terbium in a way that gets it uniformly distributed. Someday I will again find the materials paper that found it to cause a wildly anomalous but beneficial behavior.
Lastly, has HP said anything more about the "newly developed structural phase" that forms around the memristor's conductive piller? It seems like that mass could have a major effect on the electric field.
http://www.eetimes.com/electronics-news/4216057/HP-discovers-memristor-mechanism
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R G.Neale
2/17/2012 4:24 AM EST
eista-The reason why refractory metals or metal silicides and nitrides are used as phase change memory (PCM) electrodes is because during reset they need to interface with molten chalcogenide without reaction. I think the materials you suggest(SiGe,BiTe)would react and result in an unstable device. I think the IBM innovation of mixing two refractories in a composite structure is as close as it is possible to get to your suggestion at the moment.
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