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R G.Neale
eista-The reason why refractory metals or metal silicides and nitrides are used ...
rbtbob
Maybe IBM/Macronix should add a thin layer of permanently crystallized ...
PCM Progress Report No. 6: Afterthoughts
Ron Neale
2/13/2012 3:20 PM EST
Concerns about thermal crosstalk
A further processing complication was the inclusion in one orthogonal direction of thermal barriers as a contribution to both reducing reset current and reducing thermal crosstalk. To explore thermal crosstalk, the Samsung authors used a metric that considers the ratio of the total programming current applied to the array over the reset current (i.e. Ipgm/Ireset). This will have a high value when all nearest neighbors in the array are being reset and have a low value when those same devices are being set. Based only on calculation, the authors concluded that as a cumulative effect, it would take 107 write cycles with the ratio at three before the data in an adjacent reset state cell would be compromised. This was based on a measured activation energy of 3.97 eV, which also gave the data retention time of 15 months at 85°C, if accurate suitable for a PCM RAM as a PRAM.
It was this work that prompted Samsung’s dire warning with respect to the future of PCM, that thermal crosstalk is now one of the greatest concerns for PCM scaling: They stated it is “inevitable” that beyond the 20-nm node PCM memory will face thermal disturbance.
The lowest value of reset current reported was 90 μA; for a 22 nm × 7.5 nm structure; this calculates to a current density of 5.4 × 107 A/ cm2. It is interesting to note that a Samsung paper at IEDM10 presented data on a similar, but smaller, 17 nm × 7.5 nm cell with a calculated current density of 6.2 × 107A/cm2. If that trend of increasing current density with scaling continues for the dash structure, considerations of thermal crosstalk might be the least of their problems.
Finding the golden composition
One of the highlights of one of the IBM PCM papers at IEDM11 was their reporting of the discovery of a PCM material with what they termed a “golden composition.” 2 On the GST phase diagram, this composition lies approximately at the junction of the Sb-GeTe and Ge-Sb2Te3 tie lines in the direction of germanium enrichment. This new germanium-enriched Ge2Sb1Te2 (GST212) composition is considered golden because it has four significant attributes:
All else being equal, these characteristics would translate at the PCM device level into higher elevated temperature data retention, lower reset current, faster switching and a lesser tendency for voids to form during processing. Another very positive aspect of the IBM work was the inclusion of more than one device in the write/erase lifetime results.
While IBM results indicated a write/erase lifetime in the range 107 to 108 cycles, they did not address the subject of element separation. The devices were operating with a best value of reset current (500 μA) at a contact current density of about 2.5 × 107A/cm2. The devices were monolithically integrated in a 128 M-bit array.
To explore how element separation might impact the golden composition, let's consider the approximate location of the golden composition in the crystallization plane relative to GST (see figure 3). Although the starting composition of GST, shown on the lower plane phase diagram of Figure 3, is homogeneous, with accumulated write/erase cycles, element separation causes small volumes within a PCM to change in composition. The composition changes are represented by the colored dots on the second plane in figure 3. For illustrative purposes, a small circle is used to indicate regions of different compositions, although in reality the mixed compositions are spread over a larger, irregularly shaped area. What is of greatest interest is the positioning of GST at the bottom of crystallization temperature valley in the crystallization temperature surface, the third plane. It could be argued that some of the success of GST is caused by the fact that because of its location at the bottom of the crystallization temperature valley, most of the composition changes caused by element separation result in materials with a higher crystallization temperature.
A further processing complication was the inclusion in one orthogonal direction of thermal barriers as a contribution to both reducing reset current and reducing thermal crosstalk. To explore thermal crosstalk, the Samsung authors used a metric that considers the ratio of the total programming current applied to the array over the reset current (i.e. Ipgm/Ireset). This will have a high value when all nearest neighbors in the array are being reset and have a low value when those same devices are being set. Based only on calculation, the authors concluded that as a cumulative effect, it would take 107 write cycles with the ratio at three before the data in an adjacent reset state cell would be compromised. This was based on a measured activation energy of 3.97 eV, which also gave the data retention time of 15 months at 85°C, if accurate suitable for a PCM RAM as a PRAM.
It was this work that prompted Samsung’s dire warning with respect to the future of PCM, that thermal crosstalk is now one of the greatest concerns for PCM scaling: They stated it is “inevitable” that beyond the 20-nm node PCM memory will face thermal disturbance.
The lowest value of reset current reported was 90 μA; for a 22 nm × 7.5 nm structure; this calculates to a current density of 5.4 × 107 A/ cm2. It is interesting to note that a Samsung paper at IEDM10 presented data on a similar, but smaller, 17 nm × 7.5 nm cell with a calculated current density of 6.2 × 107A/cm2. If that trend of increasing current density with scaling continues for the dash structure, considerations of thermal crosstalk might be the least of their problems.
Finding the golden composition
One of the highlights of one of the IBM PCM papers at IEDM11 was their reporting of the discovery of a PCM material with what they termed a “golden composition.” 2 On the GST phase diagram, this composition lies approximately at the junction of the Sb-GeTe and Ge-Sb2Te3 tie lines in the direction of germanium enrichment. This new germanium-enriched Ge2Sb1Te2 (GST212) composition is considered golden because it has four significant attributes:
- A crystallization temperature of 250° C compared with the 150° C of the most-used GST
- A higher resistance in the crystallized state
- A more rapid crystallization
- A transition into the hexagonal crystal structure at temperatures greater than 500° C.
All else being equal, these characteristics would translate at the PCM device level into higher elevated temperature data retention, lower reset current, faster switching and a lesser tendency for voids to form during processing. Another very positive aspect of the IBM work was the inclusion of more than one device in the write/erase lifetime results.
While IBM results indicated a write/erase lifetime in the range 107 to 108 cycles, they did not address the subject of element separation. The devices were operating with a best value of reset current (500 μA) at a contact current density of about 2.5 × 107A/cm2. The devices were monolithically integrated in a 128 M-bit array.
To explore how element separation might impact the golden composition, let's consider the approximate location of the golden composition in the crystallization plane relative to GST (see figure 3). Although the starting composition of GST, shown on the lower plane phase diagram of Figure 3, is homogeneous, with accumulated write/erase cycles, element separation causes small volumes within a PCM to change in composition. The composition changes are represented by the colored dots on the second plane in figure 3. For illustrative purposes, a small circle is used to indicate regions of different compositions, although in reality the mixed compositions are spread over a larger, irregularly shaped area. What is of greatest interest is the positioning of GST at the bottom of crystallization temperature valley in the crystallization temperature surface, the third plane. It could be argued that some of the success of GST is caused by the fact that because of its location at the bottom of the crystallization temperature valley, most of the composition changes caused by element separation result in materials with a higher crystallization temperature.
Figure 3: Linking the phase diagram to write/erase element separation and upper plane crystallization temperature, highlighting the location of the germanium-enriched Ge2Sb1Te2 golden composition.
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Volatile Memory
2/15/2012 11:56 AM EST
Mr. Neale: You should stop this charade. Ovonyx will file for Chapter 11 by the end of the year. Samsung, Micron, Intel, IBM, Hynix - everybody has abandoned this thing already. The phase-change memory scam is over.
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R G.Neale
2/15/2012 4:20 PM EST
NonVolatile Memory: It is not up to me to declare the end point for the PCM project. If you read back over the six PCM progress reports and my other articles in EETimes my position is clear. I certainly think the situation now looks very bleak and I tried to convey that message. It is my view, based on published work, that the problems of: Element separation, Current Density, Scaling,Thermal Cross talk, Growing Device Complexity and Yield all weigh heavily against a bright commercial future for PCM. That does not make me, by asking questions and reporting innovative pieces of work by those who believe they can solve the problems part of a charade, or for that matter them.
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Volatile Memory
2/15/2012 5:18 PM EST
Mr. Neale: Ok, then I am declaring it. Nobody believes that PCM's "problems" can be solved. All efforts to commercialize PCM in volume have repeatedly failed since 1970. Anybody who pretends that PCM has even a slight chance to succeed is either totally uninformed or intentionally disingenuous. In other words, PCM is a techno-Ponzi.
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resistion
2/15/2012 11:07 PM EST
It is questionable to use the poor conductor, as that will up your voltage budget. You also can't RESET as fast.
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R G.Neale
2/16/2012 5:32 AM EST
resistion-If you mean the poor conductor both electrical and thermal (TaN) in the IBM/Macronix PCM electrode design then they mitigate the downside by having it spread as a thin large diameter layer at the contact point “the base of the bucket” then the (TiN) is used as the low resistance electrical conductor. I think the problem with scaling this structure is the thermally insulating sidewall layer of TaN with a thickness of 7 to 8nm will have to be reduced just as the area/volume heat loss problem worsens. If not the minimum diameter device will be 16nm plus the diameter of any TiN that is carrying the reset current. What will be very interesting next week at ISSCC2012 is to see if Samsung stay with the concave dash structure for the 8G-bit or have moved to the bucket structure.
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eista
2/16/2012 11:06 AM EST
Nice analysis, Dr. Neale
Following the thought, is the thermal-electric material good for bottom electrode (good electrical conductivity and poor thermal conductivity), such as SiGe, BiTe?
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resistion
2/16/2012 11:52 AM EST
Normally, electrical and thermal conductivity go together, supported by the electrons.
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resistion
2/16/2012 11:46 AM EST
Despite the bucket arrangement, they still have the issues, the voltage and power consumption is higher from the added resistance, which is not completely bypassed.
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kinnar
2/16/2012 6:24 AM EST
Is this Golden Composition is realizable in a practical industrial environment?
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R G.Neale
2/16/2012 9:45 AM EST
Kinnar-IBM did report a comparison test that involved baking cells from a 128M-bit PCM array with their new Golden Composition for 6 hrs at 190 degrees C and similar cells using GST225 that demonstrated its superiority give or take a few tail-bits. The GST225 based devices failing the test at 160 C test. The IBM team was very conservative in their conclusion suggesting that their work should generate further interest in material engineering as a way forward for PCM. IBM did not state the number of write/erase cycles that the devices they tested had accrued. I was more concerned about the vulnerability of the Golden Composition to element separation, especially with scaling, and the possibility, using my fig 3, that element separation might push the GC into the valley in the crystallization temperature surface where lies GST225 and compromise the performance. The answer to your question regarding the ability to withstand a practical industrial environment will only be found when the Golden Composition is used to fabricate a useful size array or the IBM 128M-bit PCM arrays are subjected to that environment.
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rbtbob
2/16/2012 11:59 AM EST
Maybe IBM/Macronix should add a thin layer of permanently crystallized chalcogenide like what HP says develops in their memristor: "...in one-to-two nanometers thick region, the film cools in an annealing-like like process which leaves the film in a fixed crystalline state that should remain that way indefinitely...." It would even out both the heat and current transfer.
AND they should dope their Golden Composition with Terbium in a way that gets it uniformly distributed. Someday I will again find the materials paper that found it to cause a wildly anomalous but beneficial behavior.
Lastly, has HP said anything more about the "newly developed structural phase" that forms around the memristor's conductive piller? It seems like that mass could have a major effect on the electric field.
http://www.eetimes.com/electronics-news/4216057/HP-discovers-memristor-mechanism
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R G.Neale
2/17/2012 4:24 AM EST
eista-The reason why refractory metals or metal silicides and nitrides are used as phase change memory (PCM) electrodes is because during reset they need to interface with molten chalcogenide without reaction. I think the materials you suggest(SiGe,BiTe)would react and result in an unstable device. I think the IBM innovation of mixing two refractories in a composite structure is as close as it is possible to get to your suggestion at the moment.
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