Design Article
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R G.Neale
rbtbob- A winner, if you qualify that claim with an acknowledgment that the 10E9 ...
rbtbob
"that the device with the confined bottom electrode was still operating at 109 ...
PCM Progress Report No. 6: Afterthoughts, part II
Ron Neale
1/20/2012 11:40 AM EST
In this second part of his phase change memory (PCM) progress report, Ron Neale explores the work done by Hynix and discusses some of the problems in the way in which claimed PCM write/erase lifetimes are reported.
The 1 Gb PCM Platform
Hynix used the 2011 IEEE International Electron Devices Meeting (IEDM11; December 5-7; Washington, DC)1 to present what was clearly top billed as a phase change memory (PCM) fabrication platform and then used it to demonstrate how, at the 42-nm node, they could fabricate 1-Gb PCM array with a 4F2 cell size.
Although the paper provided a great deal of detail by way of characteristics at the cell level, little was provided of the overall array performance, especially in terms of power dissipation, read/write data bandwidths, performance and write/erase lifetime. The 6.07-mm by 5.47-mm array was configured as 16 partitions of 64 Mb, with further subdivision of each of the 16 partitions into 32 Mats of 2 Mb. The active PCM material was stated to be a germanium-antimony-tellurium (GeSbTe) based alloy.
Shown in figure 1 is a cutaway illustration of two bits of the array. Of particular note are: a self-aligning cell structure; the poly-silicon matrix isolation device and the square, edge of film contact, to the phase change material.
Hynix addressed the challenging problem for PCM arrays of the matrix isolation device (see figure 1). It was claimed their thin film poly-silicon diode will eventually allow for the construction of 3D stacked PCM matrices; a claim that ignores any considerations of thermal cross talk discussed in part 1 of this story.
The ability to use a deposited film matrix-isolating element does offer fabrication advantages; Intel2 demonstrated the use of chalcogenide threshold switches in that role for a stacked PCM array, while IBM3 proposed the use of an ionic conduction switch as a possible matrix-isolating device. The former appears to have been abandoned and as far as I am aware the latter has not been pursued in the direction of any commercial PCM offering.
Hynix informs us that they consider the use of physical vapor deposition (PVD) and atomic layer deposition (ALD) deposition techniques will facilitate the scaling of their structure. Also, the cell structure offers a degree of flexibility in terms of the chalcogenide-electrode interface. For example, as well as the original flat square edge electrode surface, by removing some of the dielectric core (colored yellow) inside the edge electrode it is possible to produce a more confining electrode structure (see figure 2d), or even with scaling use a solid electrode surface.
Hynix1 did provide I = f (V) characteristics of the complete PCM cell, including the isolating device. From that, I have estimated an approximate value of the forward voltage drop of the poly-silicon diode, the basis of which is explained in figure 3. It is assumed that the PCM cell characteristics consist of three components: the constant voltage across the molten chalcogenide (approx 0.5 V), the forward voltage across the poly-silicon diode (approx 1 V), and the ohmic series resistance of the metalcontacts and metal interconnect. It would therefore appear that the poly-silicon diode is operating at a constant forward voltage of 1V, over the reset current range, with a current density of greater than 1 × 107 A/cm2. However, it is difficult to determine the temperature of the diode when the device is being reset.
The 1 Gb PCM Platform
Hynix used the 2011 IEEE International Electron Devices Meeting (IEDM11; December 5-7; Washington, DC)1 to present what was clearly top billed as a phase change memory (PCM) fabrication platform and then used it to demonstrate how, at the 42-nm node, they could fabricate 1-Gb PCM array with a 4F2 cell size.
Although the paper provided a great deal of detail by way of characteristics at the cell level, little was provided of the overall array performance, especially in terms of power dissipation, read/write data bandwidths, performance and write/erase lifetime. The 6.07-mm by 5.47-mm array was configured as 16 partitions of 64 Mb, with further subdivision of each of the 16 partitions into 32 Mats of 2 Mb. The active PCM material was stated to be a germanium-antimony-tellurium (GeSbTe) based alloy.
Shown in figure 1 is a cutaway illustration of two bits of the array. Of particular note are: a self-aligning cell structure; the poly-silicon matrix isolation device and the square, edge of film contact, to the phase change material.
Hynix addressed the challenging problem for PCM arrays of the matrix isolation device (see figure 1). It was claimed their thin film poly-silicon diode will eventually allow for the construction of 3D stacked PCM matrices; a claim that ignores any considerations of thermal cross talk discussed in part 1 of this story.
The ability to use a deposited film matrix-isolating element does offer fabrication advantages; Intel2 demonstrated the use of chalcogenide threshold switches in that role for a stacked PCM array, while IBM3 proposed the use of an ionic conduction switch as a possible matrix-isolating device. The former appears to have been abandoned and as far as I am aware the latter has not been pursued in the direction of any commercial PCM offering.
Figure 1: Simplified cutaway section of two bits of Hynix 1-Gb PCM.
Hynix informs us that they consider the use of physical vapor deposition (PVD) and atomic layer deposition (ALD) deposition techniques will facilitate the scaling of their structure. Also, the cell structure offers a degree of flexibility in terms of the chalcogenide-electrode interface. For example, as well as the original flat square edge electrode surface, by removing some of the dielectric core (colored yellow) inside the edge electrode it is possible to produce a more confining electrode structure (see figure 2d), or even with scaling use a solid electrode surface.
Figure 2: Confining the active region, the growing complexity
of the PCM electrode structure.
of the PCM electrode structure.
Hynix1 did provide I = f (V) characteristics of the complete PCM cell, including the isolating device. From that, I have estimated an approximate value of the forward voltage drop of the poly-silicon diode, the basis of which is explained in figure 3. It is assumed that the PCM cell characteristics consist of three components: the constant voltage across the molten chalcogenide (approx 0.5 V), the forward voltage across the poly-silicon diode (approx 1 V), and the ohmic series resistance of the metalcontacts and metal interconnect. It would therefore appear that the poly-silicon diode is operating at a constant forward voltage of 1V, over the reset current range, with a current density of greater than 1 × 107 A/cm2. However, it is difficult to determine the temperature of the diode when the device is being reset.
Figure 3: I-V Characteristics of Hynix cell with (right)
component parts that are summed in series.
The volume of material is about twice that of the PCM and is dissipating twice the power, suggesting the temperature of the diode is not too far removed from that of the PCM and must give some cause for concern.
component parts that are summed in series.
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rbtbob
2/22/2012 4:43 PM EST
"that the device with the confined bottom electrode was still operating at 109 cycles" c1- we have a winner!
"Both devices had signs of what might be considered “forming” during the first 10 or so write/erase cycles" c2- so it is a memristor?
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R G.Neale
2/22/2012 6:32 PM EST
rbtbob- A winner, if you qualify that claim with an acknowledgment that the 10E9 w/e results appear to be for one device. In addition neither of us have the elevated temperature data retention results and furthermore there may be scaling problems when you rely on thermally insulating layers to make the structure work. In IBM's other (Golden Composition) paper they provided the set/reset resistance distribution with w/e lifetime for a large number of devices. In my figure 4(f) I have provided the general form of that distribution. It would appear from their other curves, the distribution for the 10E9 device would have shown as half a decade for the low resistance state. The point I was trying to make later in the article was in the past there have been many single PCM device claims for greater than 10E9 write/erase cycles that have amounted to nothing by way of commercial products. That is why in Part 2 I produced the list of what I consider are essential requirements for reporting PCM write/erase lifetimes and why it is essential to understand the underlying cause of the different forms of the write/erase resistance curves.
Is it a memristor? I guess from what I have read elsewhere in EETimes, it is a matter of what you want to include in your definition. If the memristor requires a forming step before normal operation, that differs from normal operation then for there to be any future for the device memristor research/development will require a solution, my suggestion would be a two stage deposition of the active material. In the case of PCM the need for a forming step was negated by fabricating the device with the chalcogenide in the crystallized state.
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