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R G.Neale
rbtbob- A winner, if you qualify that claim with an acknowledgment that the 10E9 ...
rbtbob
"that the device with the confined bottom electrode was still operating at 109 ...
PCM Progress Report No. 6: Afterthoughts, part II
Ron Neale
1/20/2012 11:40 AM EST
The lifetime of more than one device
The IBM/Macronix write/erase lifetime guarantee of 108 cycles for their “golden composition” provides an opportunity to revisit the subject of write/erase lifetime. For PCM, the guarantee of 108 cycles is only of real value if it also guarantees all the other characteristics of the device will remain in tolerance at any point in the write/erase lifetime.
For me, the rules by which all claims for number of PCM write/erase cycles should be tested are:
a) A read-verify step should be included after each set/reset
b) More than one or two devices, preferably part of more than one array, are evaluated and the statistical distribution of set/reset resistance published.
c) The read voltage or current used to obtain the set/reset state resistance window should be clearly specified.
d) Write/erase lifetime testing should be carried out at both room and elevated temperature.
e) Elevated temperature data retention must be evaluated at the start, middle, and close to the end of the write/erase lifetime. Where possible, other PCM device parameters should also be presented.
f) If multiple iterative reset or set steps are used to produce a target set/reset resistance value, it should be made clear.
g) The write/erase lifetime testing should be done with the PCM device monolithically integrated into a memory array; the results for test patterns within the array are acceptable providing that is made clear.
h) For write/erase lifetime tests, in relation to the volume of material returned to the amorphous state by a given reset pulse(s), an indication of the volume fraction of that material that is crystallized during the set pulse should be provided.
I have in an earlier PCM Progress Report expressed concerns over the lack of understanding of the reasons for changes in the set/reset resistance values in the form of statistical jumps, cyclic behaviors, divergence, or the parallel changes in resistance and mixtures of those characteristics, in the results reported by different workers. Figure 4 summarizes the form or types of structure for the write/erase characteristics collected from the literature; the artificial flat curves obtained by multiple-try iterative write or erase have been omitted.
If real progress is to be made, the question that must be answered is how are the different curves related to the structure, operating conditions, and composition of the active material. Are the causes a signature of something of a fundamental nature, such as the element separation; or from the same effect the permanent crystallization of some volume of the PCM material? Are they the result of a repositioning of the central core of the active volume in the plane of the contact electrode surface or normal to it, or a result of changes at the active material-contact interface?
To help, rather than following the normal practice adopted by others of publishing the results of write/erase lifetime for one PCM device and extrapolating it to millions, IBM/Macronix4 provided a view of the distribution with write/erase lifetime, and for that they should be highly commended. They also showed that at the end of life, all devices failed open circuit at between 107 and 108 write/erase cycles. This data quickly provides the answers to one question but not all of them. The very nature of the write/erase process means there will be a statistical spread. Within the IBM/Macronix distribution, however, there are sequences where the distribution is very tight followed by sequences where the distribution becomes wide. Consideration of a single device might show this as a step function. For IBM, the first occurrence of this widening is at about 104 write/erase cycles. There have been many reports in the past, for example Lai5, that show a relatively smooth or very little by way of change in the statistical spread of resistance values early in the write/erase lifetime, followed by a sequence of much larger discontinuous changes. It is interesting to note that even these early results the change in distribution occur at 104 write/erase cycles is similar to the results of reference 4 where, from a regime of a tight distribution, a regime of larger statistical variation occurs.
The second IBM/Macronix paper6 reported write/erase lifetimes of greater than 108 cycles for a solid bottom electrode and 109 for their innovative electro-thermal contact design described earlier (see figure 2b). What is particularly interesting is the solid electrode devices failed with the reset state resistance falling steadily to short circuit, while it appeared that the device with the confined bottom electrode was still operating at 109 cycles. As far as the structure of the curves, both devices showed a significant (log curve) steady parallel reduction in set/reset resistance values. Both devices had signs of what might be considered “forming” during the first 10 or so write/erase cycles.
The reason for any serious effort to understand the form of the many types of curves in figure 3 is irrespective of the particular structure and form of the curves, in terms of operation the device continues to operate in tolerance as far as the set/reset resistance window is concerned.
The IBM/Macronix write/erase lifetime guarantee of 108 cycles for their “golden composition” provides an opportunity to revisit the subject of write/erase lifetime. For PCM, the guarantee of 108 cycles is only of real value if it also guarantees all the other characteristics of the device will remain in tolerance at any point in the write/erase lifetime.
For me, the rules by which all claims for number of PCM write/erase cycles should be tested are:
a) A read-verify step should be included after each set/reset
b) More than one or two devices, preferably part of more than one array, are evaluated and the statistical distribution of set/reset resistance published.
c) The read voltage or current used to obtain the set/reset state resistance window should be clearly specified.
d) Write/erase lifetime testing should be carried out at both room and elevated temperature.
e) Elevated temperature data retention must be evaluated at the start, middle, and close to the end of the write/erase lifetime. Where possible, other PCM device parameters should also be presented.
f) If multiple iterative reset or set steps are used to produce a target set/reset resistance value, it should be made clear.
g) The write/erase lifetime testing should be done with the PCM device monolithically integrated into a memory array; the results for test patterns within the array are acceptable providing that is made clear.
h) For write/erase lifetime tests, in relation to the volume of material returned to the amorphous state by a given reset pulse(s), an indication of the volume fraction of that material that is crystallized during the set pulse should be provided.
I have in an earlier PCM Progress Report expressed concerns over the lack of understanding of the reasons for changes in the set/reset resistance values in the form of statistical jumps, cyclic behaviors, divergence, or the parallel changes in resistance and mixtures of those characteristics, in the results reported by different workers. Figure 4 summarizes the form or types of structure for the write/erase characteristics collected from the literature; the artificial flat curves obtained by multiple-try iterative write or erase have been omitted.
Figure 4: The unexplained structure of PCM resistance curves with write/erase lifetime.
If real progress is to be made, the question that must be answered is how are the different curves related to the structure, operating conditions, and composition of the active material. Are the causes a signature of something of a fundamental nature, such as the element separation; or from the same effect the permanent crystallization of some volume of the PCM material? Are they the result of a repositioning of the central core of the active volume in the plane of the contact electrode surface or normal to it, or a result of changes at the active material-contact interface?
To help, rather than following the normal practice adopted by others of publishing the results of write/erase lifetime for one PCM device and extrapolating it to millions, IBM/Macronix4 provided a view of the distribution with write/erase lifetime, and for that they should be highly commended. They also showed that at the end of life, all devices failed open circuit at between 107 and 108 write/erase cycles. This data quickly provides the answers to one question but not all of them. The very nature of the write/erase process means there will be a statistical spread. Within the IBM/Macronix distribution, however, there are sequences where the distribution is very tight followed by sequences where the distribution becomes wide. Consideration of a single device might show this as a step function. For IBM, the first occurrence of this widening is at about 104 write/erase cycles. There have been many reports in the past, for example Lai5, that show a relatively smooth or very little by way of change in the statistical spread of resistance values early in the write/erase lifetime, followed by a sequence of much larger discontinuous changes. It is interesting to note that even these early results the change in distribution occur at 104 write/erase cycles is similar to the results of reference 4 where, from a regime of a tight distribution, a regime of larger statistical variation occurs.
The second IBM/Macronix paper6 reported write/erase lifetimes of greater than 108 cycles for a solid bottom electrode and 109 for their innovative electro-thermal contact design described earlier (see figure 2b). What is particularly interesting is the solid electrode devices failed with the reset state resistance falling steadily to short circuit, while it appeared that the device with the confined bottom electrode was still operating at 109 cycles. As far as the structure of the curves, both devices showed a significant (log curve) steady parallel reduction in set/reset resistance values. Both devices had signs of what might be considered “forming” during the first 10 or so write/erase cycles.
The reason for any serious effort to understand the form of the many types of curves in figure 3 is irrespective of the particular structure and form of the curves, in terms of operation the device continues to operate in tolerance as far as the set/reset resistance window is concerned.
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rbtbob
2/22/2012 4:43 PM EST
"that the device with the confined bottom electrode was still operating at 109 cycles" c1- we have a winner!
"Both devices had signs of what might be considered “forming” during the first 10 or so write/erase cycles" c2- so it is a memristor?
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R G.Neale
2/22/2012 6:32 PM EST
rbtbob- A winner, if you qualify that claim with an acknowledgment that the 10E9 w/e results appear to be for one device. In addition neither of us have the elevated temperature data retention results and furthermore there may be scaling problems when you rely on thermally insulating layers to make the structure work. In IBM's other (Golden Composition) paper they provided the set/reset resistance distribution with w/e lifetime for a large number of devices. In my figure 4(f) I have provided the general form of that distribution. It would appear from their other curves, the distribution for the 10E9 device would have shown as half a decade for the low resistance state. The point I was trying to make later in the article was in the past there have been many single PCM device claims for greater than 10E9 write/erase cycles that have amounted to nothing by way of commercial products. That is why in Part 2 I produced the list of what I consider are essential requirements for reporting PCM write/erase lifetimes and why it is essential to understand the underlying cause of the different forms of the write/erase resistance curves.
Is it a memristor? I guess from what I have read elsewhere in EETimes, it is a matter of what you want to include in your definition. If the memristor requires a forming step before normal operation, that differs from normal operation then for there to be any future for the device memristor research/development will require a solution, my suggestion would be a two stage deposition of the active material. In the case of PCM the need for a forming step was negated by fabricating the device with the chalcogenide in the crystallized state.
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