Design Article
Memory subsystem validation through real-time compliance test and logic analysis
Barbara Aichinger, FuturePlus Systems and Brad Frieden, Agilent Technologies
4/16/2012 3:15 PM EDT
Whether you're a designer of computer processors, computers, or mobile computing products, you are likely to be involved to some degree in the validation of a memory subsystem. New tools and techniques for testing such memories is an important topic of discussion today. This is especially true if you consider the conclusions of the extensive Google study “DRAM Errors in the Wild: A Large-Scale Field Study,” which revealed that memory failures in the field were far more prevalent than advertised and that no specific conclusion could be reached with regard to the source of the errors [1]. Since that study, new tools have emerged to shed more light on the source of errors, including a real-time protocol violation and analysis tool and a 4 Gb/s state mode logic analyzer.
Real-time protocol violation and analysis
In the area of memory debug and validation, one of the initial important tasks is probing memory signals and capturing those signals accurately to tell if the memory is behaving properly. For this example, we'll be looking at a new motherboard with a DDR3 memory sub system speed of 1867 MT/s. A DDR3 interposer probe intercepts the memory signals and brings them into the logic analyzer (see figure 1). The interposer probe is integrated with a DDR3 protocol violation and analysis tool.
Real-time protocol violation detection during the live operation of a system has only recently become available due to past inability to monitor the sensitive DDR bus with hardware and software sophisticated enough to do the job. Initial findings using the real-time protocol violation and analysis tool show that most of the emphasis placed on the DRAM parts may, for some failures, be pointing the finger in the wrong direction. The sensitive DRAM parts are designed to operate in an environment defined by JEDEC. What happens to these memory parts when the JEDEC specification, which defines how these parts are accessed or how often commands are targeted at them, is outside of the protocol specification? Laboratory and automated test equipment evaluation stresses the parts with regard to temperature, clock speed, and voltage but does not examine how the parts react to actual protocol violations.
JEDEC, the industry standard organization that includes standards for DDR memory, produces timing specifications that govern the protocol for various types of DDR memory. A protocol can be thought of as the language that the parts connected to the DDR use to talk to each other. Think of it like this: If I am speaking Mandarin to my Chinese customer and I do not say the words correctly, he will misinterpret me and may cancel his order. My inability to speak his language correctly has thus produced undesirable results. The same is true on the DDR bus. If the protocol is not followed as the chips are designed to expect, they may act in an undesirable fashion.
Real-time protocol violation and analysis
In the area of memory debug and validation, one of the initial important tasks is probing memory signals and capturing those signals accurately to tell if the memory is behaving properly. For this example, we'll be looking at a new motherboard with a DDR3 memory sub system speed of 1867 MT/s. A DDR3 interposer probe intercepts the memory signals and brings them into the logic analyzer (see figure 1). The interposer probe is integrated with a DDR3 protocol violation and analysis tool.
Figure 1: Agilent U4154A logic analyzer with FuturePlus Systems DDR3 Detective protocol violation and analysis tool, DDR3 BGA interposer probe, and FuturePlus DDR3 DIMM interposer.
Real-time protocol violation detection during the live operation of a system has only recently become available due to past inability to monitor the sensitive DDR bus with hardware and software sophisticated enough to do the job. Initial findings using the real-time protocol violation and analysis tool show that most of the emphasis placed on the DRAM parts may, for some failures, be pointing the finger in the wrong direction. The sensitive DRAM parts are designed to operate in an environment defined by JEDEC. What happens to these memory parts when the JEDEC specification, which defines how these parts are accessed or how often commands are targeted at them, is outside of the protocol specification? Laboratory and automated test equipment evaluation stresses the parts with regard to temperature, clock speed, and voltage but does not examine how the parts react to actual protocol violations.
JEDEC, the industry standard organization that includes standards for DDR memory, produces timing specifications that govern the protocol for various types of DDR memory. A protocol can be thought of as the language that the parts connected to the DDR use to talk to each other. Think of it like this: If I am speaking Mandarin to my Chinese customer and I do not say the words correctly, he will misinterpret me and may cancel his order. My inability to speak his language correctly has thus produced undesirable results. The same is true on the DDR bus. If the protocol is not followed as the chips are designed to expect, they may act in an undesirable fashion.
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