For many systems that require reliable non-volatile storage, EEPROM is the memory technology of choice. EEPROM features a robust architecture, with multiple suppliers and many years of refinement. EEPROM devices are available in a variety of industry-standard serial buses, including I2
C, SPI, Microwire, and the UNI/O bus. Due to its widespread hardware support in microcontrollers and other chipsets, and the fact that its easy signaling enables efficient implementation with minimal silicon, the I2
C bus comprises approximately 70% of the non-volatile memory market. The I2
C bus topology relies on correctly sized pull-up resistors for reliable, robust communications, however. Selecting the wrong resistor values can not only result in wasted power, but can also lead to erroneous bus conditions and transmission errors caused by noise or changes in temperature, operating voltages, and by manufacturing variations between devices.
C is a two-wire synchronous bus with the serial clock line (SCL) line used as a clock, produced by the bus master. The serial data line (SDA) is used for bi-directional data transfer. The data line is modified while the clock is in specific states, to indicate the start and stop of transmissions and avoid additional lines. The I2
C bus is built around open-collector outputs, where a device can pull a line low through a transistor to ground (see figure 1). This allows easy arbitration over control of the bus, enabling the implementation of bi-directional communications on a single data line and multi-master support. As shown in Figure 1, each line has an external resistor to the supply voltage Vdd
that pulls the line high when released or idle.
Figure 1: I2C bus topology
The three factors to consider when determining the pull-up resistor values (Rp
- Supply voltage (Vdd)
- Total bus capacitance (CBUS)
- Total high-level input current (IIH)
Let's calculate the ideal pull-up resistor values for the following example conditions:
- Supply voltage (Vdd) of 5 V
- Clock frequency of 400 kHz
- Bus capacitance of 100 pF
Supply voltage (Vdd)
First, let's take a closer look at the effect of the supply voltage Vdd
. The I2
C specification defines a voltage below VIL
, or 30% of the supply voltage, as a logical low and, likewise, above VIH
, or 70% of the supply voltage, as a logical high (see figure 2). A voltage between these two levels leads to an undefined logic level. In reality, the pin will read either logical high or low in this range, but it may vary among devices with temperatures, voltages, noise sources, and other environmental factors influencing the logic levels.
Figure 2: Specified voltage levels for logical high and low
The supply voltage limits the minimum Rp
value for which the bus can be pulled low. A strong pull-up will prevent a device from being able to bring the line sufficiently low, to ensure a logical low is detected. This is caused by the potential divider formed between the pull-up resistor and the on-resistance of the transistor to ground (see figure 3). The on resistance of the transistor is not typically specified. Instead, a maximum sink current (IOL
) is given for which the voltage drop across the transistor is below the output logical low-voltage level (VOL
Figure 3: Open-collector topology and equivalent circuit
If we apply Ohm's law we obtain the minimum pull-up resistance, allowing the bus to be pulled low:
For commercially-available I2
C EEPROM devices, the typical VOL
specification is a maximum of 0.4 V at an IOL
of 3 mA. For the case in which multiple devices are connected on the same bus, the minimum Rp
is determined by the device with the lowest sink current.