Total Bus Capacitance (Cbus)
On the SCL and SDA lines, the capacitance includes all pins, connections, PCB traces, and wire. We refer to this combination as the bus capacitance, and for long traces and cabling, this can be significant. The open-collector topology requires the external resistor to pull the line high when released. The pull-up resistor, coupled with the bus capacitance, has an RC time constant that limits the rise time. This effect grows with increasing clock frequency, because less time is available for the line to rise. If the selected resistor value is too high, the line may not rise to a logical high before it is next pulled low. This is an important consideration for designs that feature many devices on a single bus, which often have higher bus capacitance.
Figure 4: Charge time for transition between logical low to high
We can calculate bus capacitance from PCB trace lengths and published pin capacitance, or measure it using capacitance probes or smart tweezers. If a precise calculation or measurement of the bus capacitance is not possible, an overestimated worst-case reading should provide a safe maximum-resistance value.
Equation 2 is the general equation used to determine the voltage V
across a charging capacitive load as a function of time. This allows for the calculation of the time required for the bus voltage to rise to a particular value, for a specific pull-up resistance and bus capacitance.
Solving for time, we obtain
We can then calculate the time (T1
) for the voltage to rise to VIL
; the time (T2
) to rise to VIH
; and, critically, the charge time for transition between these two levels (TR
, see figure 4). Since both VIL
are products of V
dd, the equation is independent of supply voltage, since the V
dd terms cancel out.
Solving for VIL
, we obtain
Solving for VIH
, we obtain
We then calculate TR
The maximum rise time for a variety of operating voltages is specified by the I2
C standard, and is determined by the pull-up resistance. From this time and the bus capacitance, we can calculate the maximum allowable pull-up resistance (Rp
). For a 400 kHz clock frequency at 5 V, the specified maximum rise time, (TR
), is 300 ns, given the bus capacitance CBUS
of 100 pF.
Total high-level input current (IIH)
Even when no device is pulling down the line and it is a logical high, current continues to flow through the pull-up resistors. This current is caused by the leakage of the digital inputs of the devices on the bus, from low quality PCB materials, and possibly from soldering residues. Some of these cannot be foreseen, but, assuming quality materials and good manufacturing practices, the input pin leakage is dominant.
From Figure 2, the line needs to be above VIH
to be regarded as logical high, when there are no devices pulling the bus low. The leakage current limits the maximum value of Rp
, such that the voltage drop across it does not prevent the line from being pulled above VIH
. It is also prudent to allow some guard margin on the VIH
specification, to prevent noise spikes from bringing the voltage below the VIH
level. For robust operation in a high-noise environment, the I2
C specification recommends 0.2 V
dd as a suitable margin above VIH
Additional margin over logical high input level.
The leakage of digital inputs is normally given in the datasheet of devices and, for Microchip’s I2
C EEPROM devices, the maximum input leakage current (ILIEE
) is 1 µA. The minimum components for a system are a microcontroller I2
C master and an I2
C slave device. For this example, assuming a microcontroller with 1 µA input leakage (ILIMCU
) and four I2
C EEPROM devices, and allowing 100% margin, IIH
is 10 µA.
We can define the leakage current due to pin leakages for defined bus as:
Applying Ohm’s law, we can determine the maximum value for Rp
that will meet these specifications