Maximizing the sense window
The way in which BL and WL resistance are effectively reduced to provide the widest possible window for the sense amplifier also relies on parallelism. The technique is novel with respect to Samsung’s previously reported PCM array work. First, the bit lines are driven from both ends, reducing the bit line resistance to 25% of the more normal single-end method. Although for the read process, two word lines are used rather than one—in other words, the same number of cells are read but with half on one word line and half on the other—this can only be achieved in an orthogonal matrix by accessing to two tiles. The benefit is that only half the combined cell read currents flows in each word line.
This focus on the BL and WL resistance is essential because the read window for the minimum reset current is only 2x10(n)
to 4 x 10(n+1)
A.U. (see figure 2).
Figure 2: The volume of amorphous material reset results in the resistance increasing.
The positive slope of the resistance of the reset state curve would suggest to this writer that the either the volume of material being returned to the amorphous state is increasing, or for a fixed volume, the volume fraction of crystallized material in the reset cell is decreasing; figure 2 illustrates the manner in which one of those two options might be explained.
While it is any author’s privilege to use arbitrary units for, in this case, resistance and current values, it does prevent much by way of analysis of what might be happening or the consequences. The reduced size of the reset volume, or the low volume fraction reset, might offer an explanation for the poor elevated temperature data retention characteristics and why this 8-Gb PCM is now more DRAM than NVRAM.
The consequence of employing a “soft” reset mode is most likely the reason why this PCM array was in the DRAM section of the ISSCC2012 conference and not the non-volatile memory session. In reference 3, to which this work on the 8-Gb PRAM is closely linked by the authors of reference 1, the elevated-temperature data-retention time at 85°
C was reduced from better than 10 years—the required timespan for any accepted NV memory—to 15 months, making the array more appropriate for DRAM applications. In a historical context, it is worth noting that for a similar PCM structure, the previous claim was a retention time of four years at 85°
Based on other published work by Samsung on the dash PCM structure, however, I have different a observation regarding the suitability of this new 8-Gb array for even RAM, or at least some RAM applications in relation to w/e lifetime. I touched on those misgivings in an earlier PCM Progress report  and they relate to the safety of an extrapolation of a lifetime of 1015
write/ erase cycles made in reference 4 for the Samsung PCM dash structure. My rule, and that of most mathematicians, is you can invoke a logarithmic relationship and safely extrapolate it if you have data points covering at least three decades. To support their claims for the possibilities of a PCM DRAM based on w/e lifetime, the authors of the “dash” paper  took data points over two decades and extrapolated them over seven decades. Even the real data points they showed are more accurately extrapolated by a curve.
As a blind experiment, I reproduced as an exact copy the “dash” paper data and data points and without the curve or any other text data and asked three experienced engineering professionals to draw the best straight line and the best curve through the data points. None gave a curve that was anything like the one presented in the Samsung paper or even a similar straight line.
In figure 3, I have added to the original an overlay, in orange, of what in my view is a more reasonable version of this curve. To make claims and draw any conclusions from the results as presented with respect to future application possibilities was unsafe. Although the PCM lifetime, from a more realistic curve, taken as the maximum of the orange curve, that would be good enough for most NOR applications, such a curve requires at least a hypothesis to account for it. I would offer the following: There is some minimum energy at which this particular structure will no longer operate as a PCM. Referring back to figure 2 and the red curve, this would be a current value lower than that needed to make the step to the higher resistance state, so the device will fail to reset. At that point, the w/e lifetime will have dropped to zero. I would therefore postulate that for this particular PCM device structure, there is a maximum in the w/e lifetime curve at about 1012
w/e cycles for which the operating conditions are optimized so as to minimize reset failure.
Figure 3: Plot of write/erase cycle lifetime versus program energy for PCM devices shows realistic estimated performance for PCM.