Editor’s note: This work was first presented at the 2011 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2012 (San Francisco, CA; December 10-12), click here. Abstract
We successfully developed highly scalable and cost-effective PCRAM technology based on 0.007 µm2
, 84-nm pitch) sized novel cell scheme. The chip size and density are 33.207-mm2
and 1 Gb. The device functionality and reliability were clearly demonstrated through fully integrated chip, which showed a promising feasibility for productive NVM applications.Introduction
So far, PCRAM (phase change RAM) research has been focused on mobile application such as NOR and/or LPDDR2 NVM [1-3]. PCRAM can also merge the attractive points of NAND and DRAM in one chip, which makes a prospective potential for the new application concept like storage-class memory (SCM) to reduce the performance gap between DRAM and SSD. Furthermore, PCRAM can be alternatively compatible for working memory and storage type application. Therefore, it can be started in the middle point of system architecture which moves to memory-like and/or storage-like. In recent, industry is also considering feasibility for various new applications. However, PCRAM production cost is still questionable. In this paper, we report a technological platform and attractive breakthrough which should be significantly addressed to implement cost-competitive and highly scalable PCRAM.Key features and full integration
Figure 1 shows the design layout, fundamental circuit information, and components in the proposed PCRAM chip.
Figure 1: PCRAM chip design layout and fundamental organization.
Table 1: Key features of the device and process technology.
The chip supports various circuit functions such as including the standard interfaces for mobile applications and advanced future PCRAM specifications. Key features are summarized in Table 1. The unit cell size is 84 nm × 84 nm (= 0.007 µm2
) based on the 84 nm-pitched 4F2
(F = 42 nm). The 33.207 mm2
chip includes 1-Gb cell arrays which consist of 16 partitions × 64 Mb. The Gex
based alloying elements are used as phase change cell material. Two-level Cu, W, and Al interconnections are employed in memory cell array and core/peripheral circuit.
Figure 2: Photograph of a fully integrated 1 Gb PCRAM chip.
Figure 3: Schematic description of the full process architecture, 4F2 cell layout and novel self-aligned structure for combination of cell heater and access device on metal W/L.
Figure 2 reports a fully integrated PCRAM chip image which contains cost-effective technology breakthrough including advanced 4F2
cell structure, access device concept on metal W/L (no strapping contact within cell mat), switch device scheme under cell block, and novel self-aligned process as well as a simplified architecture as shown in figure 3. Figure 4 clearly shows cross sectional images of the fully integrated structure. In addition, the proposed technologies can be also a fundamental platform and stepping stone for cost-effective multilayer PCRAM cell stacking.
Figure 4: Cross sectional (X and Y axis) TEM images of the processed cell and core/peripheral area.Phase change cell characteristics
Electrical switching behavior as shown in figure 5 was demonstrated by I-V characteristics in amorphous reset, and crystalline set state cell. Upon the application of a reset current pulse, the I-V curve initially displayed high resistance, and subsequently switched to its original low resistive state at a threshold voltage of 1.90 V.
Figure 5: I-V curve of threshold memory switching behavior in reset and set state cells including an access device.
Figure 6 shows resistance change as a function of programming current pulses. Starting with the initial set state, a large increase in resistance was observed upon applying 30 ns pulses above a threshold of 140 µA. Resistance was saturated above 200 µA. Similarly, a significant resistance reduction was also observed upon applying 300-ns pulses above a threshold value of 80 µA.
Figure 6: Programming current pulse-induced resistance change behavior of the cell combined with access device.
The R-I curve completely confirmed two distinct memory states with resistance varying over two orders of magnitude. Well separated resistance states for reset and set were also obtained as shown in figure 7.
Figure 7: Reset and set state resistance distribution after programming current pulse.