Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 1

Multi-die DRAM packaging
One way to potentially reduce the area required for the memory system is to use multi-die DRAM packaging. While the idea is not new, most multi-die DRAM packages in production today are designed with depth expansion in mind: The data signals are connected in common and one device is selected at a time when reading or writing. The depth-expanded architecture is optimized for constructing high-capacity, multi-rank DIMMs for server applications, with the goal of increasing memory capacity. It is the wrong approach for the Ultrabook platform.

For Ultrabook applications, memory devices must be interconnected to allow simultaneous parallel operation with data pins spatially separated from one another (width expanded). Consider a 64-bit memory subsystem. It requires the interconnection of four wide-word (x16) DRAM die in a single quad-die package (QDP). The problem is that the configuration generates switching current transients that are higher than for the depth-expanded server QDP case. Not only does the architecture of the server version of QDP limit reads or writes to a single die at a time, there are only four data output drivers switching simultaneously rather than the 64 data bus drivers needed for the Ultrabook application. As a result, careful attention must be given to thermal and electrical properties of the package.

To derive benefit by eliminating HDI technology from the Ultrabook, the cost premium introduced by the switch to QDP from four single-die packaged DRAM must remain small. An appropriate QDP has to meet strict performance requirements in a number of areas: cost, thermal, electrical, and cost of use in a system (PCB complexity).

Quad-die DRAM packages
The most common QDP in production today is the face-up wirebonded stacked-die configuration. In this scheme, four die are stacked vertically separated by silicon spacer die. Wirebonds connect the bonding pads to pads on the substrate below (see figure 2). Because mainstream DDR3 DRAM modules have bonding pads along the center spine, a redistribution layer (RDL) must be applied to the die to relocate the pads to the edges so they can be used in a stacked-die configuration.
Figure 2: Quad-die package (QDP) consists of spacer layers (pale blue) sandwiched between die (gray). A redistribution layer (RDL, green) relocates the pads to the edges of the board so they can be used in a stacked-die configuration.

The RDL process is a wafer-level build-up process. In its simplest form, it consists of depositing metal on the top surface of the wafer, patterning it using photolithography, and then covering with a passivation layer that is photo-imaged to expose the bonding pads. It is an expensive process, costing about as much per die to apply an RDL as the entire assembly cost of the standard single-die package DRAM component [1].

The assembly process flow for the RDL QDPconsists of many costly steps. Starting with RDL-patterned wafers, substrate strips, and dummy die, a die-attach machine places a live memory die face up on each substrate site followed by a dummy die placed atop the live die. Next, the strip passes into a wirebond machine and the die is wirebonded to the substrate. The sequence is repeated three times. In the fourth and final die attach pass, there is no spacer die used.

From a thermal perspective, the RDL QDP presents the challenge of removing heat from a seven--layer stacked structure. Because most of the thermal flux flows in the Z direction through the stack of die, the operating temperatures of the center pair of die are significantly elevated compared to a single die structure. For width-expanded devices used in Ultrabook application, the temperatures are even higher since all four die are cycled in lockstep.

From an electrical perspective, the RDL adds capacitance and resistance to each signal lead as well as inductance. The inductance of the power distribution traces interacts with switching currents to induce voltage drops that degrade the power integrity of the die, which reduces operating voltage margin. Resistance further aggravates such margin. The capacitance of the RDL adds loading to switching signals causing reduction of timing margin.

An RDL QDP is thicker than a face-down wirebonded SDP because it has four live die plus three spacers in the stack. It also has top side wirebond loops that must be encapsulated, further adding to the package height. Since trends in portable computing include a reduction of thickness, any increase of Z height for component packaging is undesirable. These characteristics prompted the search for an alternative.