Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 1

DIMM in a package technology for Ultrabook
Using four 2-Gb DDR3 DRAM die of x16 organization, the memory functionality of a 1-GB SODIMM is contained in a single 243-ball package with a 17 x 17 x 1 mm size using 0.8 x 0.8 mm ball pitch. To construct the quad face down (QFD) package, two DRAM die are mounted face-down on a multi-layer organic window substrate along with two spacer die. Atop this lower structure, two more DRAM die are mounted rotated 90° relative to the lower die (see figure 3).

All four die are wirebonded in a single pass through individual substrate windows. The complexity, and hence the cost, of the assembly process is considerably simpler for the QFD than the stacked QDP (see figure 4).



When a detailed model of the assembly process was compared it was found that manufacturing the QFD cost less per die than a single die package (see figure 5). The key reason is because of the process consolidation resulting in fewer total process steps to assemble a given number of DRAM die.

Because there are no topside wire loops, the package requires minimal topside encapsulation. The vertical stackup consists of two die plus a four layer substrate permitting the package to be manufactured less than 1-mm thick.

Electrically, the QFD package is superior to the RDL-based stacked-die package because the four die are arranged face down with short wirebonds connecting to the substrate without RDL. The critical data and data strobe substrate routings are kept short for high speed operation. The command/address (C/A) signals are placed in the central portion of the package and appear in duplicate. Architecturally, pairs of memory die are operated in lockstep, with each receiving its own C/A bus signals. This enables the four-die package to be operated as a single x64 memory system or as two independent x32 memory systems. Having two sets of C/A bus signals also offers significant PCB layout benefits as will be explained in the PCB layout section below.

Limiting the stack height to only two die versus the four-die stack of the conventional RDL QDP architecture significantly enhances the thermal characteristics of the package. Additional thermal benefit is derived by the lateral displacement of the DRAM die versus the stacked arrangement of the conventional.

Figure 6 presents the results of a thermal simulation showing temperature profiles for the stacked QDP and the QFD models shown in Figure 2 and Figure 3.The models were simulated in accordance with JESD 51-6 for forced convection with 1 m/s airflow.  In the models, all four die are simultaneously being accessed with each having a power dissipation of 0.5 W. The simulations show that the die in the QFD have significantly lower operating temperature for any airflow condition versus the stacked QDP.

PCB layout considerations
A key goal of the DIMM in a package technology is to enable the design of low-cost but high performance, dense PCBs while avoiding layout-directed HDI PCB fabrication technology. The ballout of the new packaging platform is key to accomplishing this.

A major goal for the ballout is that it be simple to use on a densely-packed double-sided PCB and not require the use of HDI technology to achieve PCB routing goals. To facilitate efficient use on double-sided assemblies, the ballout was made axi-symmetric about the Y axis when viewed looking through the package with the key at the upper left.

The QFD package’s ball array is partially depopulated to accommodate the wire bonding windows. That region divides the BGA into two regions: an inner and an outer region. The inner region contains the C/A bus signals and power signals, while the outer region contains the output data (DQ) and data strobe signal (DQS) signals, various strobes and power signals. There are two sets of C/A bus signals arranged into two mirror imaged groups of columns in the central region. When a same type package is placed on the opposite side of a PCB in a clamshell configuration, these signals can share vias in the breakout region for the CA bus signals with no need for a cross-tie pattern as is needed for single die DRAM packages. The use of the redundant mirror-imaged CA bus enables this characteristic.

The outer region contains the DQ and DQS signals along with other signals. When placed on opposite sides of the PCB, DQ and DQS signal vias can be shared straight through the PCB, enabling a simple dual-rank layout configuration featuring electrically-short interconnections.

Power connections are designed to be shared as well. The result is a very simple and uncluttered layout when using this ballout scheme (see figure 7). As can be seen by inspection, the ballout is symmetric about the Y axis, leading to significant simplification of the PCB, as will be shown in detail.

Part two of this feature will show DIMM-in-a-package technology in action.

References:
1. Crisp, R. et al: “High Performance Multi-Die DRAM Packaging for High-Speed Server Applications using Dual Face Down Architecture with Wirebond Assembly Infrastructure.” Paper presented at ISMP2011 in Seoul Korea on October 12, 2011.

About the author
Richard Crisp is vice president and chief technologist at Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. Crisp is responsible for product strategy, development, and promotion of Invensas’ semiconductor packaging technologies with a particular focus on DRAM packaging.




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