Design Article
Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 2
Richard Crisp, Invensas Corp.
6/4/2012 12:46 PM EDT
In part one of this two-part feature, the author discussed the way ultra-slim notebook PCs are changing the way memory is used in portable clients and how quad face down (QFD) packaging can deliver the memory functionality of a 1-GB small-outline dual in-line memory modules (SODIMM) in a single 17 x 17 x 1 mm, 243-ball package. Part two presents a case study to illustrate the characteristics of the technology.
To illustrate the advantages of the DIMM-in-a-package technology, a detailed layout routing study was undertaken. Starting with a production Ultrabook product, the goal was to determine if the QFD package version of the DIMM-in-a-package structure could permit the design to be converted to a non-high-density-interconnect (HDI) PCB while maintaining the overall form factor.
The CPU-memory channel layout is one of three factors that forced the use of HDI technology. The other two were the packaging used for the peripheral control hub and embedded controllers: Both require HDI for the package breakout. Both of these components are offered in packaging that doesn’t require HDI for breakout but the packages require a larger footprint on the PCB. Reducing the footprint of the memory subsystem offers the potential for accommodating these larger components that have no layout-driven requirement for HDI PCB technology.
The reference design was arranged as two channels of a single rank of 2Gbit x8-organized DRAM in 16 single-die packages (SDPs). Electrical design constraints impose both maximum and minimum trace lengths for the various nets used to interconnect the DRAM to the CPU. Nearly 100 mm of lead-in trace is required between the memory controller and the first DRAM package for the command/address (C/A) bus signals, for example. Additionally serpentine routing must be used with the memory array to satisfy electrical design rules.
Because the ballout of the SDPs did not permit sharing of vias with opposite side components, congestion in the breakout region made it impossible to use through-board vias and meet all of the requirements for trace length control. As a result, the design required HDI technology and blind vias to satisfy layout density requirements.
Reducing cost
The QFD package enabled a cost-reduced PCB design. The architecture chosen was a dual-channel dual-rank configuration. It was designed to be fabricated on a low cost conventional 12-layer through-hole via, glass-epoxy PCB.
Combining four x16-organized DRAM die into a single 17 x 17 mm package reduced the overall XY area of the memory region of the new PCB design by about 40% compared to the HDI-based reference design (see figure 8). The area saved was sufficient to permit substitution of the peripheral control hub and embedded controller IC packages to lower-cost, larger-footprint versions that do not require the use of HDI for PCB breakout. As a result, the new packaging technology met the goal of conversion to non-HDI PCB technology. The CPU and memory routing regions for the original and new PCB designs are shown in Figure 8.
There is both a cost and schedule benefit arising from using the simpler PCB technology. Converting to non-HDI PCB cuts PCB cost to 25% of the original, a savings of more than $10 per system. PCB prototype fabrication time is reduced from three weeks to five days. Both are very attractive benefits in the high-volume highly competitive PC hardware business.
To illustrate the advantages of the DIMM-in-a-package technology, a detailed layout routing study was undertaken. Starting with a production Ultrabook product, the goal was to determine if the QFD package version of the DIMM-in-a-package structure could permit the design to be converted to a non-high-density-interconnect (HDI) PCB while maintaining the overall form factor.
The CPU-memory channel layout is one of three factors that forced the use of HDI technology. The other two were the packaging used for the peripheral control hub and embedded controllers: Both require HDI for the package breakout. Both of these components are offered in packaging that doesn’t require HDI for breakout but the packages require a larger footprint on the PCB. Reducing the footprint of the memory subsystem offers the potential for accommodating these larger components that have no layout-driven requirement for HDI PCB technology.
The reference design was arranged as two channels of a single rank of 2Gbit x8-organized DRAM in 16 single-die packages (SDPs). Electrical design constraints impose both maximum and minimum trace lengths for the various nets used to interconnect the DRAM to the CPU. Nearly 100 mm of lead-in trace is required between the memory controller and the first DRAM package for the command/address (C/A) bus signals, for example. Additionally serpentine routing must be used with the memory array to satisfy electrical design rules.
Because the ballout of the SDPs did not permit sharing of vias with opposite side components, congestion in the breakout region made it impossible to use through-board vias and meet all of the requirements for trace length control. As a result, the design required HDI technology and blind vias to satisfy layout density requirements.
Reducing cost
The QFD package enabled a cost-reduced PCB design. The architecture chosen was a dual-channel dual-rank configuration. It was designed to be fabricated on a low cost conventional 12-layer through-hole via, glass-epoxy PCB.
Combining four x16-organized DRAM die into a single 17 x 17 mm package reduced the overall XY area of the memory region of the new PCB design by about 40% compared to the HDI-based reference design (see figure 8). The area saved was sufficient to permit substitution of the peripheral control hub and embedded controller IC packages to lower-cost, larger-footprint versions that do not require the use of HDI for PCB breakout. As a result, the new packaging technology met the goal of conversion to non-HDI PCB technology. The CPU and memory routing regions for the original and new PCB designs are shown in Figure 8.
Figure 8: 3-6-3 HDI PCB implementation using single die packages (top) and 12-layer standard process PCB implementation using quad die package with Invensas Ballout (bottom, yellow lines included for size comparison reference).
There is both a cost and schedule benefit arising from using the simpler PCB technology. Converting to non-HDI PCB cuts PCB cost to 25% of the original, a savings of more than $10 per system. PCB prototype fabrication time is reduced from three weeks to five days. Both are very attractive benefits in the high-volume highly competitive PC hardware business.
|
|
|
|
|
Navigate to related information