Detailed comparison of PCB layouts
A close examination of the memory package breakout regions reveals the reasons for the improvement. Figure 9 shows the two designs: and a HDI PCB SDP on the left and a QFD package on the right. In these views, the outer layers and vias are shown for each layout. In the figures, the outlined region shows the package outline that, considering double-sided clamshell assembly, accommodates two die in the basic footprint. The QFD package footprint accommodates eight die. The reduction of area is clear: The entire memory system needs 16 die to produce the necessary capacity.
Figure 9: HDI PCB SDP memory breakout (left), top-bottom versus a standard-process PCB QFD breakout (right) shows outer layers and vias for each layout. The yellow lines show the package outline that, considering double-sided clamshell assembly, accommodates two die in the basic footprint (left) or eight die in the QFD package footprint (right).
In Figure 10 the full set of routing layers is shown. Again the QFD package is on the right.
Figure 10: HDI SDP memory footprint (left, all layers) versus normal process QFD Footprint (right, all layers). The yellow lines show the package outline that accommodates two die in the basic footprint (left) or eight die in the QFD package footprint (right).
A close examination reveals that none of the vias needed for the SDPs are shared but that most of the vias needed for the new QFD package are shared. The mirror imaged redundant C/A bus region requires no cross tied routing, greatly reducing the wiring density in the breakout region. These are the key reasons why the DIMM-in-a-package ballout simplifies the PCB design.
The ballout developed for the QFD package has a depopulated square ring of balls needed for the bonding windows required for assembly of center-bonded DDR3, DDR4, and x16 LPDDR3 die. When using face-up or flip-chip assembly, no such bonding windows are needed so these depopulated ball positions can be used to carry additional power and signal connections specific to other types of memory.
From a functional signal perspective, LPDDR3 and DDR3 have identical signals on the data side, meaning the ballout is 100% compatible with the signals in the outer region of the ballout. LPDDR3 differs from DDR3 on the address and command side. Instead of sampling these signals on the rising edge of the clock, LPDDR3 samples a smaller number of signals on both edges of the clock to extract the address and command information.
A controller that offers co-support of DDR3 and LPDDR3 multiplexes the LPDDR3 C/A signals onto the existing DDR3 C/A bus signals in the PHY with a particular mapping. By duplicating that mapping in the DIMM-in-a-package ballout, a PCB can be designed to accommodate either DDR3 or LPDDR3 on the same board as a build time option when using a controller that offers co-support (see figure 11).
Figure 11: PCB-Level Co-support of DDR3x and LPDDR3
GDDR5 die are also supported by the ballout. In that configuration, two GDDR5 devices are arranged in a face-up stacked arrangement like for the LPDDR3 case. This provides an x64 high-speed graphics memory system in a single package. This is targeted for the needs of discrete graphics subsystems used in notebook PCs where form-factor is critical.
Even the proposed master-slave TSV die stacks are supported by this versatile ballout. Figure 12 shows example structures that can use the DIMM in a Package technology.
Figure 12: Co-support of different memory types
Carrying co-support to the PCB level, DIMM-in-a-package technology significantly simplifies material logistics for the OEM. One PCB design is used for the low end DDR3-based machine or the high end ultra-long-battery life LPDDR3 version.