Design Article
Multi-die DRAM packaging technology drives down Ultrabook platform cost – part 2
Richard Crisp, Invensas Corp.
6/4/2012 12:46 PM EDT
Other design benefits
The benefits of the redundant mirror-imaged C/A bus connections in the middle region of the new ballout are not limited solely to simplification of the PCB design. Another layout benefit is in the design of the package substrate. Each C/A signal ball now routes to two instead of four die. The average length of the route is shorter versus having a single placement in the center of the substrate. The net effect is a reduction of electrical signal length for improved signal integrity at high frequency, and a savings of two or more substrate routing layers. The layer savings reduces package thickness and cost and reduces bond wire lengths, which saves significant amounts of gold. The thinner substrate also simplifies the wirebonding process by reducing the depth the bonding tool must travel into the window during bonding.
From an architectural perspective, the redundant C/A bus connections permit the new structure to be used as a single channel of x64 memory or two independent channels of x32 memory (see figure 13): The difference is in the PCB wiring. Most of the ultra-low-power CPUs used for tablet computers use dual 32 bit memory channels. The DIMM in a Package provides a single package memory solution for these applications. By placing a second package on the opposite side of the PCB and interconnecting virtually all signals, a second rank of memory can added to provide a simple but effective capacity expansion option.
Signal Integrity Without HDI
One electrical benefit of HDI is the avoidance of stubs when vias are used to move a signal from one layer to another. The blind via technology permits the via to only extend to the desired layer with no stub extending beyond.
Conventional through-board vias can have significant stub lengths when a via is used to transition a signal from the top layer to a nearby layer. In that case the stub is the longest possible: nearly a complete board thickness (see figure 14). These undesirable effects can be tolerated in many cases by adopting design rules that avoid certain layer transitions. If a signal needs to transition from a top layer trace to another, for example, then if it is sent to the next-to-bottom layer, the length of the via stubs are kept to the thickness of a layer, typically less than 0.1mm.
While HDI can typically permit a higher speed PCB to be developed, careful design using conventional PCB technology can often deliver a better price/performance ratio. A key goal in the PC business is attaining optimum performance with the discipline of a cost-justified approach; i.e., if a 10% cost reduction can be achieved for a 2% performance reduction, that would be an attractive option.
For the highest possible performance with LPDDR3, point-to-point signaling may be used with controllers offering co-support of LPDDR3 and DDR3. In this case, the controller provides a duplicate copy of the LPDDR3-mode C/A information on the upper field of the command /address bus. Each of the controller’s duplicate C/A signals then connects to only one of the C/A bus connections on the DIMM-in-a-package using HDI PCB technology, maintaining point-to-point signaling at the expense of sacrificing PCB-level co-support (see figure 15).
The memory capacity can be doubled by resorting to a point to two point configuration by placing devices in clamshell configuration (see figure 16).
New ultra-slim form factors for portable client computers have displaced the SODIMM in favor of soldered-down memory on the motherboard. Current systems primarily use conventional single die DRAM packaging on costly HDI PCBs to meet PCB form-factor and electrical design constraints.
A new DIMM-in-a-package technology simplifies the design challenges for this new class of client computers. Coupled with a versatile and efficient ballout, the approach drives greatly simplified PCB designs while consolidating the manufacturing test infrastructure for several DRAM technologies used in multi-die wide-word applications including DDR3, DDR4, LPDDR3 and GDDR5.
About the author
Richard
Crisp is vice president and chief technologist at Invensas Corporation,
a wholly owned subsidiary of Tessera Technologies, Inc. Crisp is
responsible for product strategy, development, and promotion of
Invensas’ semiconductor packaging technologies with a particular focus
on DRAM packaging.
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The benefits of the redundant mirror-imaged C/A bus connections in the middle region of the new ballout are not limited solely to simplification of the PCB design. Another layout benefit is in the design of the package substrate. Each C/A signal ball now routes to two instead of four die. The average length of the route is shorter versus having a single placement in the center of the substrate. The net effect is a reduction of electrical signal length for improved signal integrity at high frequency, and a savings of two or more substrate routing layers. The layer savings reduces package thickness and cost and reduces bond wire lengths, which saves significant amounts of gold. The thinner substrate also simplifies the wirebonding process by reducing the depth the bonding tool must travel into the window during bonding.
From an architectural perspective, the redundant C/A bus connections permit the new structure to be used as a single channel of x64 memory or two independent channels of x32 memory (see figure 13): The difference is in the PCB wiring. Most of the ultra-low-power CPUs used for tablet computers use dual 32 bit memory channels. The DIMM in a Package provides a single package memory solution for these applications. By placing a second package on the opposite side of the PCB and interconnecting virtually all signals, a second rank of memory can added to provide a simple but effective capacity expansion option.
Figure 13: Configuration options for DIMM-in-a-package.
Signal Integrity Without HDI
One electrical benefit of HDI is the avoidance of stubs when vias are used to move a signal from one layer to another. The blind via technology permits the via to only extend to the desired layer with no stub extending beyond.
Conventional through-board vias can have significant stub lengths when a via is used to transition a signal from the top layer to a nearby layer. In that case the stub is the longest possible: nearly a complete board thickness (see figure 14). These undesirable effects can be tolerated in many cases by adopting design rules that avoid certain layer transitions. If a signal needs to transition from a top layer trace to another, for example, then if it is sent to the next-to-bottom layer, the length of the via stubs are kept to the thickness of a layer, typically less than 0.1mm.
Figure 14: Via stub design rules with non-HDI PCBs.
While HDI can typically permit a higher speed PCB to be developed, careful design using conventional PCB technology can often deliver a better price/performance ratio. A key goal in the PC business is attaining optimum performance with the discipline of a cost-justified approach; i.e., if a 10% cost reduction can be achieved for a 2% performance reduction, that would be an attractive option.
For the highest possible performance with LPDDR3, point-to-point signaling may be used with controllers offering co-support of LPDDR3 and DDR3. In this case, the controller provides a duplicate copy of the LPDDR3-mode C/A information on the upper field of the command /address bus. Each of the controller’s duplicate C/A signals then connects to only one of the C/A bus connections on the DIMM-in-a-package using HDI PCB technology, maintaining point-to-point signaling at the expense of sacrificing PCB-level co-support (see figure 15).
Figure 15: Point-to-point signaling option for highest speed LPDDR3 using HDI PCB.
The memory capacity can be doubled by resorting to a point to two point configuration by placing devices in clamshell configuration (see figure 16).
Figure 16: Point to two Points signaling option for highest speed LPDDR3 using HDI PCB.
New ultra-slim form factors for portable client computers have displaced the SODIMM in favor of soldered-down memory on the motherboard. Current systems primarily use conventional single die DRAM packaging on costly HDI PCBs to meet PCB form-factor and electrical design constraints.
A new DIMM-in-a-package technology simplifies the design challenges for this new class of client computers. Coupled with a versatile and efficient ballout, the approach drives greatly simplified PCB designs while consolidating the manufacturing test infrastructure for several DRAM technologies used in multi-die wide-word applications including DDR3, DDR4, LPDDR3 and GDDR5.
About the author
Richard
Crisp is vice president and chief technologist at Invensas Corporation,
a wholly owned subsidiary of Tessera Technologies, Inc. Crisp is
responsible for product strategy, development, and promotion of
Invensas’ semiconductor packaging technologies with a particular focus
on DRAM packaging._________________________
Did you find this article of interest? Then visit the Memory Designline, where we update daily with design, technology, product, and news articles tailored to fit your world. Too busy to go every day? Sign up for our newsletter to get the week's best items delivered to your inbox. Just click here and choose the "Manage Newsletters" tab.
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