Improved memory throughput using serial NOR flash - part 1

Editor’s note: This work was first presented at the Embedded Systems Conference (ESC) 2012. You can register to view other papers from the proceedings here. For more information about ESC 2013 (San Jose, CA; April 22-25), click here.

NOR flash memory remains the preferred non-volatile technology for discrete memories in embedded systems. For some applications, NOR usage is migrating away from the parallel NOR bus to products based on the lower-pin-count serial peripheral interface (SPI) to optimize the memory subsystem. Many systems using NOR-based SPI memories have reached 108 MHz bus clock rates using a QuadIO (x4) interface to achieve a 54 MB/s sustained read throughput while retaining compatibility with the original interface specified more than 25 years ago. The latest SPI-NOR product releases are incorporating a DDR-read operation and reaching throughputs of up to 80 MB/s. As system-level read throughput requirements continue to increase, a number of strategies have been deployed to optimize the SPI interface for higher performance. This article describes both system-level and memory-device strategies that have been deployed to allow higher SPI read throughputs.

History
SPI was introduced in the early 1980s by Motorola and continues to be popular throughout the embedded market. The original interface (see figure 1) has an efficient four-pin (CS#, SCK, SI, SO) bus structure that rapidly achieved market dominance over the proprietary Inter-Integrated Circuit (I²C) bus from Philips Semiconductor and Microwire interface from National Semiconductor introduced during the same period. Initial EEPROM products for all three of the interfaces used low-cost eight-pin DIP and SOIC packages.




The early EEPROM offerings had limited operating frequencies by today’s standards: 1 MHz for SPI and Microwire, and 100 KHz for I²C. While the initial offerings had modest clock rates, by the time NOR flash had emerged as the dominant non-volatile memory (NVM) technology in the mid 1990s, it was clear that read throughputs would become a first order value proposition.

The SPI bus has evolved over time, improving read throughputs by increasing both clock rates and bus width. Bus width increased from the original x1 to x2, and finally a x4 interface (see figure 2). The evolution of the SPI bus width has been accomplished by retasking the original six SPI bus signals to support the x2 and the x4 bus widths without increasing the overall pin count. Today’s NOR-based QuadIO SPI memories commonly reach 108 MHz clock rates to achieve a 54 MB/s sustained read throughput. Clock rates of 133 MHz are starting to appear on some SPI memories. The SPI bus interface is used on virtually all higher-density NOR flash offerings.




Comparison with alternative NOR flash memory interfaces
Two of the more significant criteria used when considering NOR flash devices are the sustained read throughput and the number of pins used for the bus interface. Figure 3 compares different NOR flash bus interfaces and their respective read throughputs. The legacy parallel interfaces (async, page, and ADP burst) all require more than 40 pins with an address/data multiplexed version of the parallel bus (ADP) having around 30 pins. Historically, the parallel interfaces have provided higher read throughputs, but recent advances in SPI bus performance have significantly closed the throughput gap.




The read throughput comparison in figure 3 shows that SPI NOR exceeds the abilities of the asynchronous NOR bus and approaches the level of the page mode interface. This comparable performance to async and page products is especially relevant for the many embedded chipsets that do not support either of the burst NOR interfaces.  Recent product announcements of 133 MHz QuadIO (66 MB/s) and 80 MHz DDR-QuadIO (80 MB/s) tilt the performance in favor of the SPI interface wherever the parallel burst and page mode interfaces are not available.