Design Article
Improved memory throughput using serial NOR flash - part 2
Cliff Zitlaw, Spansion Inc.
6/18/2012 12:51 PM EDT
Double data rate (DDR)
The next step in transaction compression was the introduction of Double Data Rate (DDR) transfers during both the address/mode and data portions of a read transaction (see figure 13). The command needs to remain Single Data Rate (SDR) to support legacy protocol constraints but once the device recognizes a DDR request the remaining transaction can be performed in a DDR fashion.
DDR read transactions also supported the implied command usage of the mode bits that allows the elimination of the eight bit command at the beginning of a read transaction. The DDR read transaction using the command elimination strategy reduces the command/address overhead to only three clocks (see figure 14).
Preamble for data training
Capturing read data is a fundamental problem for common clock memory interfaces. As data is returned from the memory device, data placement is skewed significantly with respect to the clock. This is not a significant problem at lower frequencies where the data from the memory has enough time to reach the host prior to the capturing clock edge but as the clock period shrinks it becomes harder to return data in a timely manner. The problem is compounded when the data is presented in a DDR fashion with a new data value output by the memory every half clock cycle. Modern DRAM and NAND memories have dealt with this issue by including a source synchronous clocking signal that allows the memory to toggle a data strobe with the same characteristic skew present in the output data. The strobe returns to the host and is used to indicate when the target read data is present on the bus.
The problem for the SPI bus is that all of the six legacy bus signals are used for the high-performance Quad IO Read operation. An alternative host data capture strategy is to incorporate a Data Learning Pattern (DLP) in the read sequence that will help to indicate when the target data is valid on the bus (see figure 15). The DLP is presented during the unused Dummy Cycles that occur immediately before the target data is output by the memory. The DLP is used by the host controller to identify the characteristic skew between the common clock and the data output of the memory. While the DLP sequence is presented, the host determines the optimal skew required to successfully capture the target data. All of the read data for a particular transaction is captured with the same skew that was indicated during the DLP training. The DLP training process is performed during every read transaction to assure that all system level and device level skews are understood by the host prior to data capture.
DDR read transactions using the DLP also supported the implied command usage of the mode bits that allows the elimination of the eight bit command at the beginning of a read transaction. The DDR read transaction with DLP using the command elimination strategy also reduces the command/address overhead to three clocks (see figure 16).
Future improvements
The need for higher read throughputs is emerging in many applications and NVM manufactures continue to develop strategies to meet these increasing demands. While the SPI bus has some room for read bandwidth increases any dramatic improvement will require a fundamental reevaluation of the legacy SPI interface.
Next: Bond pad locations
The next step in transaction compression was the introduction of Double Data Rate (DDR) transfers during both the address/mode and data portions of a read transaction (see figure 13). The command needs to remain Single Data Rate (SDR) to support legacy protocol constraints but once the device recognizes a DDR request the remaining transaction can be performed in a DDR fashion.
Click image to enlarge
Figure 13: DDR Quad IO Read
DDR read transactions also supported the implied command usage of the mode bits that allows the elimination of the eight bit command at the beginning of a read transaction. The DDR read transaction using the command elimination strategy reduces the command/address overhead to only three clocks (see figure 14).
Click image to enlarge
Figure 14: DDR Quad IO Read with implied command
Preamble for data training
Capturing read data is a fundamental problem for common clock memory interfaces. As data is returned from the memory device, data placement is skewed significantly with respect to the clock. This is not a significant problem at lower frequencies where the data from the memory has enough time to reach the host prior to the capturing clock edge but as the clock period shrinks it becomes harder to return data in a timely manner. The problem is compounded when the data is presented in a DDR fashion with a new data value output by the memory every half clock cycle. Modern DRAM and NAND memories have dealt with this issue by including a source synchronous clocking signal that allows the memory to toggle a data strobe with the same characteristic skew present in the output data. The strobe returns to the host and is used to indicate when the target read data is present on the bus.
The problem for the SPI bus is that all of the six legacy bus signals are used for the high-performance Quad IO Read operation. An alternative host data capture strategy is to incorporate a Data Learning Pattern (DLP) in the read sequence that will help to indicate when the target data is valid on the bus (see figure 15). The DLP is presented during the unused Dummy Cycles that occur immediately before the target data is output by the memory. The DLP is used by the host controller to identify the characteristic skew between the common clock and the data output of the memory. While the DLP sequence is presented, the host determines the optimal skew required to successfully capture the target data. All of the read data for a particular transaction is captured with the same skew that was indicated during the DLP training. The DLP training process is performed during every read transaction to assure that all system level and device level skews are understood by the host prior to data capture.
Click image to enlarge
Figure 15: DDR Quad IO Read with Data Learning Pattern
DDR read transactions using the DLP also supported the implied command usage of the mode bits that allows the elimination of the eight bit command at the beginning of a read transaction. The DDR read transaction with DLP using the command elimination strategy also reduces the command/address overhead to three clocks (see figure 16).
Click image to enlarge
Figure 16: DDR Quad IO Read with Data Learning Pattern and elimination of command
Future improvements
The need for higher read throughputs is emerging in many applications and NVM manufactures continue to develop strategies to meet these increasing demands. While the SPI bus has some room for read bandwidth increases any dramatic improvement will require a fundamental reevaluation of the legacy SPI interface.
Next: Bond pad locations
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