Bond pad locations
Signal assignments on the original eight lead DIP and SOIC packages have historically mandated the relative positions of the signals on an SPI memory die. The legacy pad placement may be attractive for wire bonding but is non-optimal from a signal skew perspective. Significant care needs to be taken during the design of high speed SPI memories to minimize the IO to IO skew while simultaneously maximizing the data valid period (see figure 17).
Click image to enlarge
Figure 17: Bond pad placement on 256 MB SPI memory
While leaded packages (SOIC) are still driving SPI volumes, a significant number of products are shipping in FBGA packages. Signal assignment in FBGA packages is more flexible than for leaded packages and it is likely that future on-die signal placement will be optimized for higher operating speeds without the legacy packaging constraints.
A wider bus?
During the evolution of the SPI bus from x1 to x2 to x4 the legacy six signal interface (CS#, SCK, SO, SI, WP, HOLD) has been fully retasked for improved bus throughput (CS#, SCK, IO[3:0]). No more signals are available to improve bus performance. One of the obvious possibilities for improvement is a departure from the six-pin constraint with an increase in the signal count to support an x8 bus width (CS#, SCK, IO[7:0]).
An x8 SPI interface has a few of drawbacks that are worth consideration:
- In modern production test environments many devices are tested simultaneously. An increase in the number of pins will result in less parallelism and cause in a higher per unit test cost.
- The higher pin count will require a new package, the legacy 8 lead devices will not support a x8 interface. A SO16 package is popular for SPI-NOR flash memory devices but there is an associated higher cost for the larger package.
- The move to a x8 bus will only result in a doubling of bus throughput. The resulting throughput might be attractive in the immediate future but there would be little enthusiasm for taking the next step to a x16 bus width.
- SPI controllers on the host SoC would need to be upgraded to support the increased bus width and an additional four pins allocated for the new interface.
- One issue in the SPI-NOR market is that there are significant differences in the bus protocol between the different manufacturers. The basic subset of x1, x2 and x4 read operations have been grandfathered in but a new interface with the required new commands would need alignment between manufacturers if an x8 interface were to gain market traction.
Even though there are obstacles for an upgraded SPI bus protocol the need for improved read throughput will cause a higher performance interface to be developed. This need for a next generation SPI interface might be an activity for an industry standards organization like JEDEC. SPI standardization through JEDEC is an activity that would likely be well received by both customers and manufacturers.
SPI NOR will continue to be the low cost leader due to minimal pin count, low cost packaging, highly parallel testing infrastructure and perhaps most importantly an efficient bus interface that minimizes die area. Fundamental SPI bus constraints set the stage for a next-generation NOR interface that will “rebalance” low pin count with higher read throughput. Even after a low-pin-count next-generation, high-performance interface comes to market, the legacy NOR-based SPI offerings will continue to be viable for a wide swath of applications. At this point there is every reason to believe that the SPI bus will enjoy another 25 years of life as an NVM interface.
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