Understanding DDR SDRAM timing parameters

Many engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM.

To begin with, let's first understand how different DDRs are rated or classified. If we want to buy a DDR module from market, we have to consider many parameters like size, speed, timing specs, brand etc. So, we have many options to choose from. To have a better understanding of these ratings, let’s see how these are presented to the buyers. Below is the picture of a DDR SDRAM module (figure 1).


As seen in figure 1, the module reads DDR3-1600MHz, PC3-12800. So, what does this mean? In DDRx-yyyy, "x" represents the technology generation (example: DDR2, DDR3, DDR) and "yyyy" represents the DDR clock rate or more appropriately the data rate. DDR (double data rate), as the name suggests, transfers two chunks of data per clock cycle and hence achieve twice the performance as compared to the memory without this feature. It is for this reason that DDR are rated with twice the clock rate at which they function, i.e., the data rate.

Usually, DDRx-yyyy convention is followed for the memory chips. But memory chips are not available as such. They are soldered onto tiny PCBs and are termed as memory modules, the speed of which is described as PCx-zzzz. In PCx-zzzz, “x” represents the same technology generation and "zzzz" is the maximum bandwidth, i.e., maximum transfer rate in MBytes/s.

Maximum Transfer Rate = clock x number of bits / 8

Since memory modules transfer 64 bits at a time, the “number of bits” will be 64.

Therefore, the formula can be simplified as:

Maximum Theoretical Transfer Rate = clock x 8

Also, one can see the operating voltage and the size of the module mentioned on the memory module. In figure 2, one can easily distinguish between the memory chips and the memory module. The tiny black entities embedded onto the green color PCB are the memory chips, and the complete integrated circuit is the memory module.


So, figure 1 throws out the following information. The memory module consists of memory chips which work at real clock of 800 MHz—i.e., its data rate is 1600 MHz and supports a maximum possible data transfer rate of 12800 MB/s between the controller and the module. It has a capacity of 8 Gb.
 
Now coming to the timing parameters, we notice 9-9-9-25 and 9-9-9-24 mentioned on the memory module in figure 1 and figure 3, respectively.

So, what exactly does the timing A-B-C-D (or sometimes CLA-B-C-D) mean? It’s intriguing how sometimes two memory modules with same maximum transfer rate, running at same clock frequency achieve different performances. Its because of different timing parameters. The memory timings are given through a series of numbers; as in figure 3, 9-9-9-24.


These numbers are a measure of the time the memory chip takes for performing internal operations. It indicates the amount of clock cycles taken by the memory to perform the internal operations. The smaller the number, the faster the memory. The operations that these numbers indicate are as following: CL-tRCD-tRP-tRAS(-CMD). To understand these operations better, let’s first understand the SDRAM access procedure.