DDR SDRAM access
Memory is organized into a grid-like pattern, with "rows" and "columns." The data stored comes in blocks and is defined by the coordinates of the row and column. The steps for the memory controller to access data in SDRAM follow in order:
First, the SDRAM is either in idle state or executing the previous operation. The controller issues the "active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles. After the delay, column address and either "read" or "write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). However, the read data isn't available until a few clock cycles later, because the memory is pipelined
. When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued.
Now we can study the detailed definition of various timing parameters.
CAS Latency (CL)
: CAS Latency (Column Access Strobe Latency), also known as "Access Time," is the most important memory parameter and is the first of the series of numbers. It is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins. In DDR SDRAM it is specified in clock cycles, while in asynchronous DRAM it is specified in nanoseconds.
RAS to CAS Delay (tRCD)
: tRCD stands for row address to column address delay time. Inside the memory, the process of accessing the stored data is accomplished by first activating the row then the column where it is located. tRCD is the time required between the memory controller asserting a row address strobe (RAS), and then asserting a column address strobe (CAS) during the subsequent read or write command. The lesser this time, the better it is, as the data will be read sooner.
RAS Precharge (tRP)
: Whenever a new row is to be activated for the purpose of accessing a data bit, a command called “Precharge” needs to be issued to close the already activated row. RAS Precharge time, tRP is the number of clock cycles needed to terminate access to an open row of memory, and open access to the next row.
Active to Precharge Delay (tRAS)
: After an “Active” command is issued, another "Precharge" command cannot be issued until tRAS has elapsed. So, tRAS is the minimum number of clock cycles needed to access a certain row of data in the memory between the data request (Active) and the Precharge command. Basically, this parameter limits when the memory can start reading (or writing) a different row.
: All the four parameters work with memory real clock i.e. half the rated clock. A memory with CL=4 need not be slower than the one with CL=3. It all depends on what clock frequency both of them work and accordingly, absolute latencies can be calculated for each of the two.
For better understanding, the timing diagram of a memory with timing parameters 3-3-3-10 (assumed) is presented in figure 4.
Click image to enlarge
Figure 4: Timing diagram of DDR SDRAM, 3-3-3-10
To conclude the article, we can summarize the timing parameters as below:
This article originally appeared on the EE Times Europe website.
- CAS Latency (CL) is the time it takes to read the first bit of memory from a DRAM with the correct row already open.
- The time to read the first bit of memory from a DRAM without any active row is tRCD + CL.
- The time to read the first bit of memory from a DRAM with the wrong row open is tRP + tRCD + CL.
- The number of clock cycles required between an "Active" command and issuing the "Precharge" command is tRAS.