Simulated LRS and HRS distribution
Examination of the simulated Vo configuration confirms that similar gap
distances can be achieved by these two programming schemes, thus
explaining the exponential voltage-time relationship  of the
In Figure 16, the simulated HRS distribution
after 1000-times pulse cycling is correlated with their Vo
configuration. It is revealed that the lognormal spread of HRS is due to
the variation of the average gap distances, while the tail bits of HRS
are due to Vo generation near the electrode at the end of a programming
pulse (see the last current jump of figure 10 as an experimental
Figure 16: Simulated HRS distribution after
1000-times pulse cycling. The lognormal distribution is due to the
Gaussian distribution of the average gap distances. The tail bits are
due to new Vo near the electrode generated at the end of the pulse (see
Figure 10 for an experimental example of tail bit creation).
reduce the tail bits of HRS, the reset-verify technique  can be used
(see figure 17), but this may introduce more over-reset bits of HRS and
consequently more tail bits of LRS . Therefore, controlling the gap
distance in the reset process is crucial to overcoming the over-reset
Figure 17: Simulated LRS and HRS distribution with
reset-verify technique. The purpose of multiple reset pulses is to
decrease the new Vo generation probability at the end of a single pulse.
With a maximum of three trials, above 99.9% HRS meet the criterion
(1MΩ). The over-reset bits may in turn cause more tail bits of LRS,
however, which is undesired.
We propose using an additional
buffer oxide layer that has a larger oxygen ion migration barrier (Em)
to confine the switching in the active oxide. By tuning the
active/buffer oxide thickness, the over-reset bits of HRS are reduced
(see figure 18). This leads to a smaller number of tail bits of LRS as
well; however, the tail bits of HRS still remain.
Simulated LRS and HRS distribution of a bi-layer structure. The buffer
layer has Em=1.2 eV, the active layer has Em=1 eV, and the total oxide
thickness remains the same (10 nm). We see that 1.5 nm active layer is
effective for reducing the over-reset bits and the tail bits of LRS, but
it does not help eliminate the tail bits of HRS.
the bi-layer structure with the reset-verify technique is thus expected
to achieve both uniform LRS and HRS distribution (see figure 19).
Experimentally, uniformity improvement has been observed in the bi-layer
structure such as HfOx
 and HfOx
19: Simulated both uniform LRS and HRS distribution are achieved by
combining a bi-layer structure with the reset-verify technique.
The main achievements of this work include:
- A self-consistent TAT solver was developed to quantify the electronic conduction
- A stochastic oxygen ion generation/recombination/migration model was established to quantify the ion processes
- The variations of DC I-V characteristics and pulse transient waveform were reproduced
- Switching features such as current overshoot, multilevel capability and the exponential voltage-time relationship were revisited
- The current fluctuation during the reset process was attributed to the competing forces between Vo generation and recombination
- The origin of HRS tail bits is clarified
device structure with active/buffer bi-layer oxides combined with
reset-verify was proposed to solve the over-reset and tail bits
This paper provides new understanding of the
physical origin of the switching parameter variations and provides
device design guidelines to improve the switching uniformity in a large
memory array. The development of the simulation tool opens up an
opportunity to systematically study the variability of the metal oxide
We thank Yi Wu, Yang
Chai, J. Provine and Cambridge Nanotech for the device fabrication. This
work is supported in part by DARPA SyNAPSE, NSF ECCS 0950305, the NRI
of the SRC through the NSF/NRI Supplement to the NSF NSEC Center for
Probing the Nanoscale, the member companies of the Stanford NMTRI, and
the C2S2 Center of the FCRP, an SRC subsidiary. S. Yu is additionally
supported by the Stanford Graduate Fellowship.
1. H. Y. Lee et al., IEDM 2010, pp. 460-463.
2. S.-S Sheu et al., ISSCC 2011, pp. 200-202.
3. R. Waser et al., Adv Mater. vol. 21, pp. 2632-2663.
4. S. Yu et al., VLSI-TSA 2011, pp. 106-107.
5. N. Xu et al., Symp. VLSI Technol. 2008, pp. 100-101.
6. S. Yu, et al., Appl. Phys. Lett., vol. 99, 063507 (2011).
7. S. Yu, et al., IEDM 2011, paper 12.1.
8. N. F. Mott et al., Electronic Processes in Non-Crystalline Materials, 1979.
9. S. Yu et al., IEEE Electron Device Lett., vol. 35, p. 1455 (2010).
U. Russo, IEEE Trans. Electron Devices, vol. 56, pp. 193-200 (2009).
11. L. Vandelli, International Memory Workshop 2011, pp. 119-122.
12. Animation video available @ http://nanowiz.stanford.edu/
username: stanfordnano; password: iedm2011
13. S. Yu et al., Appl. Phys. Lett., vol. 98, 103514 (2011).
14. J. Lee et al., IEDM 2010, pp. 452-455.
15. W. J. Zhu, et al., IEEE Electron Device Lett., vol. 23, pp. 97-99 (2002).
About the authors
Ximeng Guan received his Ph.D. degree and B.E. degree from Tsinghua University, China in 2010 and 2005, both with honor. He is now a postdoctoral scholar at the Stanford Nanoelectronics Group. His research interests are in the modeling of nanoscale electronic devices. Currently he is working on the modeling of resistive non-volatile memory, energy efficient electronic devices, and MOSFETs with high-mobility channels. He has authored or co-authored 24 journal and conference papers.
Shimeng Yu received the B.S. degree from Department of Microelectronics, Peking University, China, in 2009, and the M. S. degree from Department of Electrical Engineering, Stanford University, USA, in 2011, where he is currently working toward the Ph.D. degree. His past research actives includes the simulation of the parameters fluctuation in nanoscale transistors and SRAM cells. He has been working on the fabrication, characterization, and modeling of the emerging resistive switching memory devices and their applications for neuromorphic computation system since 2008.
H.-S. Philip Wong received the B.Sc. (Hons.) in 1982 from the University of Hong Kong, the M.S. in 1983 from the State University of New York at Stony Brook, and the Ph.D. in 1988 from Lehigh University, all in electrical engineering. He joined the IBM T. J. Watson Research Center, Yorktown Heights, New York, in 1988. In September, 2004, he joined Stanford University as Professor of Electrical Engineering. His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging.