Anti-fuse memory provides robust, secure NVM option

E-fuse NVM
E-fuse is an electronically programmed read-only memory bit comprising a polysilicon fuse in the silicide or poly layer of an SoC, Programming the fuse requires a dc pulse a few milliamps in amplitude and several microseconds in duration. This high current programs the fuse by dramatically increasing the resistance of the polysilicon link.

For high-k metal gate (HKMG) processes, common for 32 nm processes and below, the e-fuse needs to be implemented as a metal fuse. The operating principle is similar to that of the poly fuse above, but in this case the high programming current breaks the metal link, just as for a standard safety fuse. The HKMG e-fuse needs comply with electromigration rules and overcome any unwanted side effects of metal debris such as metal shreds resulting from the blown fuse. To date, metal fuses have not reached reliability comparable to that of poly fuses in terms of data retention and their areas have not scaled like previous poly fuse technology.

The e-fuse is well suited for small capacity NVM needs of up to 4 kbits. Available from most foundries, e-fuse is often provided at low cost. Small quantities of e-fuse are ubiquitous in SoC designs to provide memory repair, for containing trimming data for analog mixed signal circuits, and for configuration and ID. Because of the prevalence of this memory, large fabless chip companies often have their own proprietary e-fuse implementations.

For small-capacity solutions not requiring field updates or security, e-fuse is a viable solution. For capacities greater than 8 kbits, it is not as viable because of the size of the bit cell, thus it cannot scale economically. Implemented in standard logic CMOSprocesses, it requires no additional mask layers or process steps and thus scales with process evolution. The memory is unique from ROM in that it is programmed electrically at final test, thus allowing individual chips to contain unique data, for example, trimming data for analog mixed-signal circuits, or repairing memory on board the SoC. The e-fuse suffers the same security vulnerabilities as ROM. Note that the e-fuse is foundry specific and as such cannot be used across different foundries, thus reducing design portability.

Embedded flash and floating gate memory
Both ROM and e-fuse are one-time programmable NVMs and are ill-suited to applications that require re-programmability, such as program code that changes to fix bugs or add new features, encryption keys that must frequently be erased and rewritten with new ones, or general data that requires frequent updates. For these requirements, flash memory provides a better solution.

Flash technology is the most flexible of the NVM options available. It is widely used for program storage in microcontrollers embedded in a larger SoC. Flash memory can be written during final test as well as changed at any time thereafter. The storage mechanism for flash memory is based on floating gate that must be built on top of a logic process. When charged with electrons, this holds the bit of data until an erase operation removes the stored charge.

One problem with flash memory is high manufacturing cost resulting from the additional mask layers—up to 15 in a 90 nm process—that must be added to a standard logic CMOS process, plus an additional UV-erase and bake manufacturing step. The rule of thumb is that adding flash to a design only makes sense if the amount of flash being integrated represents a high percentage of the SoC’s total real estate.

The other problem with flash is it does not scale with the process technology. At each smaller process node, the amount of charge contained in the floating gate decreases and the increasing leakage inherent in smaller process geometries makes it difficult for the floating gate to maintain a charge. To mask these drawbacks, additional logic circuits are needed for bit-error correction and for bit cell sensing. Below 90 nm, however, a solution is not readily available.

There are alternative floating gate technologies that provide the re-programmability of flash with fewer or no additional mask layers. The floating gate is created during manufacture in the same plane on the chip as the select, program, and read transistors, making it simpler to build than flash. It affords an order of magnitude fewer read-write cycles (endurance) than flash, and requires UV erase and bake manufacturing steps. In addition, both floating gate and flash have significant security vulnerabilities with regard to reverse engineering or hacking.