As the name already indicates, anti-fuse uses a different bit-cell compared to fuse (or e-fuse) NVM. With anti-fuse the unprogrammed bit is logic “0” and the programmed bit is logic “1”; for fuse (or e-fuse) NVM, it is the exact opposite. Anti-fuse NVM enables field programming, as it requires much less programming current than fuse NVM.
Anti-fuse NVM became practical when standard logic CMOS arrived at the 180-nm process node. This was the first process node for which the gate oxide breakdown voltage was less than that of the junction breakdown voltage. With each successively smaller process geometry, the gate oxide breakdown voltage continues to decrease along with transistor dimensions and the oxide thickness. Thus, anti-fuse technology has the benefit of improving with each new process generation: more bit cells per area, less power consumed to write and read the memory, and increased reliability as a result of less power consumed during operation.
Another benefit derived from the creation of the anti-fuse is that the bit cell is very difficult to detect using the passive and active reverse engineering techniques that prove effective against all the other memories described thus far. Programming the bit cell causes a breakdown in the gate oxide that is highly localized. Since gate oxide breakdown is statistical in nature, the location of the breakdown varies as it can break at the channel, halo, or LDD regions, thus making it very difficult to predict or to detect using conventional reverse engineering techniques (see figure 1).
Figure 1: Two-transistor anti-fuse bit cell.
As can be seen in the illustration, the anti-fuse circuit is produced just as any other logic CMOS gate would be created, making the NVM easy to manufacture using any logic CMOS process, including the newer generation of high-K metal gate implementations. Thus, no additional mask steps or manufacturing handling steps (like UV-erase and bake) are required to build the memory.
As with all the other NVM technologies except ROM, anti-fuse is programmed at final test, thus it can be utilized for configuring product variations from a single parent. This requires less inventory of different dies and facilitates fast and flexible response to changing market requirements, different products SKUs can be realized at tester speed.
One application for anti-fuse is for repair function in the manufacture of DRAM where the anti-fuse configures spare DRAMs memory locations to replace non-functioning locations detected during final test, thus improving DRAM yields significantly.
Anti-fuse also has the ability to be programmed in the field using an on-board charge pump or using Vdd supplied via a pin from the SoC’s power rails. This capability is desirable in designs that allow field programming of the trim data for the analog-mixed signal circuits that can drift over time.
Programming the anti-fuse memory in the field points to the capability of the memory to provide a limited amount of re-programmability achieved by over-provisioning the amount of memory in the array and using the spare cells to replace existing data with revised content. At process geometries of 45-nm and smaller, the amount of multi-time programming can reach as high as 1000 cycles.
Another application that takes advantage of this field programming capability is multimedia set top box SoCs that need to be able to program or reprogram a secure encryption key. Anti-fuse is attractive for this application, facilitating key revocation/replacement as well as security.
The other option anti-fuse offers for set-top box (and other high security applications) is the means to obscure the secure data content of the set-top box (or other devices) in the field in such a way that the original data can no longer be detected at all. Programming additional or all bits in the memory array to a “1” obscures the original content, providing a “destroy upon tamper event” option.
Perhaps the most important advantage of anti-fuse NVM is its ability to resist all existing reverse engineering methods. Techniques such as using current measurements to determine the data pattern are unsuccessful due to the implemented sensing architecture. Hackers cannot determine the pattern of the word being read. Invasive techniques including backside attacks or SEM passive voltage contrast are unsuccessful because the individual bit cells cannot be isolated within the memory array (see figure 2, bottom).
Figure 2: Anti-fuse bit cells cannot be hacked using passive, semi-invasive, and invasive methods such as SEM techniques (bottom). method shown.
It is also difficult using de-processing such as chemical etching or mechanical polishing to locate the oxide breakdown. In a cross section or a top view, it is difficult to determine which bit is programmed (see figure 3).
Figure 3: Another advantage of anti-fuse NVM lies in the difficulty of distinguishing between program and unprogrammed bit cells, in either cross-section (top) or top view (bottom).
Anti-fuse NVM, even when implemented as compact, large-capacity arrays in advanced processes, is not suitable for NVM applications that have very high endurance (re-write) requirements such as 10,000 cycles that are typical for eFlash. The anti-fuse silicon area required for such endurance (number of possible re-writes) would be too large to be cost effective.
Of the embedded NVM memories commercially available, ROM, e-fuse, flash/floating gate, and anti-fuse, all have their particular strengths and weaknesses. As process geometries reach 28 nm and smaller and the need for secure storage increases, however, anti-fuse technology begins to emerge as the desirable alternative, offering more secure storage while scaling with each new generation of process.
About the author
Bernd Stamme is director for marketing and applications at Kilopass Technology. He has more than 15 years of experience in the IP and semiconductor industry. Prior to Kilopass, he was the director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets. Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.
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