As with most storage technologies, NAND flash vendors are constantly being pushed to reduce cost and increase density. One way the industry has responded is by packing more than one bit in a single flash storage cell. Known as multi-level cell (MLC) memory, this technology allows for a doubling or tripling of the data density with just a small increase in the cost and size of the overall silicon. This increase in density and decrease in cost per bit does come with its own tradeoffs, however, which have to be considered within the context of the application.
Industrial, military, and avionic applications impose very different demands in terms of environmental stresses, data endurance requirements, and expected usable life compared to consumer products such as USB thumb drives, memory cards for digital cameras, or even SSDs for consumer laptops and tablets. We’ll examine those tradeoffs, with an emphasis on how they affect the reliability of storage targeted at industrial, military and avionic applications.Flash cell operation
Before discussing the differences between single-level cell (SLC) and MLC NAND flash, it is important to understand what makes up a flash cell. Each cell consists of a single transistor, with an additional “floating” gate that can store electrons (see figure 1).
Figure 1: A basic flash cell consists of a transistor with a (floating) gate capable of storing electrons.
The cell operates as follows. For reading, the gate is electrically disconnected. The conductivity between the source and drain is then a function of the amount of charge on the floating gate. A voltage difference is set up between the drain and the source, Vd – Vs and is varied to determine the threshold voltage Vt
when current flows between source and drain. The threshold voltage represents the amount of charge on the gate. A large amount of charge is used to represent logic ‘0,’ and a small amount of charge used to represent logic ‘1.’
Writing is done by applying the programming voltage Vp to the gate and grounding the channel, which sets up an electric field such that electrons are attracted to the surface of the channel. Some of these collide or encounter the barrier with enough energy to tunnel through the insulating layer. These electrons are captured by the floating gate. Erasing is the opposite operation, with the gate grounded and with Vp
applied to the channel to create an electric field with the opposite polarity. This attracts electrons back to the channel, many of which will have enough energy to cross the insulating barrier. This process is called Fowler-Nordheim Tunneling.
This explains one of the key challenges of flash technology—while it’s easy to attract electrons to the floating gate one cell at a time, it’s difficult to get them to leave. Reversing the process requires putting the channel at a voltage that could disturb adjacent cells, since the channel is common to many cells. For this reason, flash is erased in blocks, not a word or bit at a time. The blocks are sized by the flash manufacturer in order to balance silicon area (since each erase block carries a fair amount of overhead circuitry) and ease of use. Because of the logic structure of NAND flash, the flash must also be written or read in fairly large pages, typically 1 K to 4 KB. These pages are written from or read to a page buffer, from which individual byte reads or writes are done. Each erase block contains between 32 and 128 pages.
This also helps explain why flash cells can only be written a limited number of times before they wear out. While many of the electrons travel with enough energy to cross the insulating oxide, some have enough to cross the barrier between the channel and oxide, but not enough to go all the way to the floating gate. These get trapped in the oxide. With each write/erase cycle, more electrons get trapped, which reduces the conductivity difference between the “programmed” and “erased” states. We will discuss this further when we talk about the endurance differences between SLC and MLC.