Single-level cell (SLC) operation
SLC NAND flash cells operate pretty much as described in the basic operation above. Both writing and erasing are done gradually to avoid over-stressing, which can degrade the lifetime of the cell by increasing the number of electrons trapped in the oxide or by causing oxide damage. Essentially, a write or erase is attempted, then stopped, and the cell is tested to see if the erase/write was successful. If not, it is reattempted, possibly with stronger or longer pulses. This is done several times until the operation time exceeds the specification and the cell is declared “bad.”
Since there are only two states, a cell represents only one bit value. Each bit can have a value of “programmed” or “erased.” A “0” or “1” is determined by the threshold voltage Vt of the cell (see table 1). The threshold voltage can be manipulated by the amount of charge put on the floating gate of the flash cell.
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Table 1: The bit value of the cell translates as either programmed or erased.
Placing a charge on the floating gate will increase the threshold voltage of the cell. When the threshold voltage is high enough, the cell will be read as programmed (see figure 2). No charge, or a threshold voltage of less than the minimum programmed voltage, will cause the cell to be sensed as erased. As the cell wears, these two distributions move closer together, narrowing the difference between the values of Vt for erased and programmed. When they overlap, it is impossible to distinguish between programmed and erased states.
Figure 2: The threshold for each determines whether a cell is read as programmed or erased. As electrons get trapped in the oxide, the conductivity difference between the two states. When the curves overlap, the system can no longer distinguish between programmed and erased states.
2-bit per cell MLC
It is also possible to store more than one bit at each cell location by using multiple threshold voltages to encode multiple states (see table 2).
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Table 2: State table describes the amount of charge in the floating gate of the flash cell.
These four states yield two bits of information. After block erasure, the cell is in the fully erased state. By increasing the number of electrons stored on the floating gate, the cell can be brought from fully erased to partially erased, to partially programmed, and, finally, to fully programmed. This is done in the same manner as described earlier for gradually programming the SLC cell, by applying write pulses, then sensing the amount of charge to ensure that the cell was properly programmed.
The gaps between the various states of an MLC are much smaller than the gap between the two states of an SLC NAND flash (see figure 3). Another way to describe this is that the signal-to-noise ratio of an MLC cell is much less than for an SLC cell. Because of this, a more powerful error correction code is needed to correct for errors introduced by noise, which can be either true electrical noise or noise induced by a trapped charge in a cell that has seen many program/erase cycles.
Figure 3: Because the gaps between the various states of an MLC are much smaller than the gap between the two states of an SLC NAND flash, the devices need more powerful error correction code.
3-bit MLC flash
The MLC concept can be extended beyond just two bits; devices with three bits per cell (referred to by many as three-level cell or TLC) are currently commercially available. Three bits actually yield 23
or eight levels (see table 3). Some companies have begun to refer to devices with three bits per cell as MLC-3, which is a better way to characterize it.
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Table 3: Memory cells with three bits yield 23 or eight levels.
At this point, the difference in charge stored on the floating gate between the levels is on the order of 100 electrons or less, so for the time being, TLC is the practical limit of extending this concept, although there are companies beginning to experiment with four bits per cell. In fact, SanDisk has recently announced a four-bit-per-cell NAND flash for USB thumb drives. All of the issues with two bits per cell become even more difficult with a greater numbers of bits.