Design Article
SLC vs MLC: Which works best for high-reliability applications?
Charlie Cassidy, TeleCommunication Systems
7/16/2012 4:43 PM EDT
Choosing the right memory for high-reliability applications
Now that we've reviewed the differences between MLC and SLC technology, let’s compare their specifications to make further distinctions between the two grades with an eye toward the requirements of military, avionics and industrial applications (see table 4). These applications have more stringent demands on temperature range and the reliability of the storage. The cost of lost data in a critical mission is much higher than in consumer use. When life and property are on the line, or when you only get one shot at success, reliability is everything.
Performance
Since the same basic flash cell is used for SLC and MLC NAND flash, MLC can more than double the density with almost no die size penalty, and hence no manufacturing cost penalty beyond possibly yield loss. In fact, because of the large consumer demand for MLC NAND flash for digital cameras, tablets, and smart phones, MLC enjoys economies of scale that give it a cost per bit cost less than half that of SLC.
The read bandwidths between SLC and MLC are comparable: SLC can read a 1KB page in about half the time that MLC can read a 2KB page. In general, the available bandwidth of a solid-state drive is more related to the controller architecture and design than to the speed of the flash. MLC NAND flash technology does pay a price in terms of access speed, however. Access and programming times are two to three times slower than for the single-level design. For many consumer applications, this speed difference will be virtually undetectable.
Endurance
The endurance of SLC NAND flash is 10 to 30 times more than MLC NAND flash (see figure 4). This, and the difference in operating temperature, are the main reasons why SLC NAND flash is considered industrial-grade, and MLC NAND flash is considered consumer-grade. The endurance difference is also generally not a problem in consumer use. For example, a USB drive application that used the 10,000 write/erase cycles would enable the user to completely write and erase the entire contents once per day for 27 years – well beyond the life of the hardware. On the other hand, a data logging application that was constantly writing telemetry or sensor data might completely write the contents of the drive 10 times a day, leading to an endurance of only 2.7 years.
Error rate
The error rate for MLC NAND flash is 10 to 100 times worse than that of SLC NAND flash and degrades more rapidly with increasing program/erase cycles. This is driven by the very narrow margin between voltage threshold levels in MLC.
There are four principal error mechanisms that affect flash data reliability:
1. Program disturb
2. Read disturb
3. Leakage
4. Charge trapping
Program disturb is caused by the stress to unselected cells in the same erase block as the cell being programmed. These unselected cells can either be adjacent bits on the same page or the corresponding bit on adjacent pages. This voltage stress can cause a small amount of charge to be deposited on the floating gates of these adjoining cells, thus weakly programming them. While not a major problem for SLC NAND flash, the addition of a small amount of charge can cause a shift between the levels in an MLC NAND flash cell. This can be a particular problem with repeated program cycles of adjoining cells. For this reason, well-designed flash controllers program pages sequentially within an erase block. This also explains why MLC NAND flash cannot withstand multiple writes per page.
Read disturb is caused by the voltage difference between the selected page being read and adjacent, unselected pages. This can stress the cells in the adjacent pages and cause a small amount of charge to be transferred to the gate of an erased cell, weakly programming them; again, this is a larger problem for MLC NAND flash cells then SLC cells, since a very small voltage shift can affect the value stored.
Leakage of the charge on the floating gate is the phenomenon that leads to a limit on the data retention time for a cell. The floating gates can lose electrons at a very slow rate, on the order of an electron every week to every month. With the various values in multi-level cells only differentiated by 10s to 100s of electrons, however, this can lead to data retention times that are measured in months, rather than years. This is one of the reasons for the large difference between SLC and MLC data retention and endurance. Leakage is also increased by higher temperatures, which is why MLC NAND flash is generally only appropriate for commercial temperature range applications.
Next: Charge trapping
Now that we've reviewed the differences between MLC and SLC technology, let’s compare their specifications to make further distinctions between the two grades with an eye toward the requirements of military, avionics and industrial applications (see table 4). These applications have more stringent demands on temperature range and the reliability of the storage. The cost of lost data in a critical mission is much higher than in consumer use. When life and property are on the line, or when you only get one shot at success, reliability is everything.
Click image to enlarge
Table 4: A comparison of the features and capabilities of SLC versus MLC memory.
Performance
Since the same basic flash cell is used for SLC and MLC NAND flash, MLC can more than double the density with almost no die size penalty, and hence no manufacturing cost penalty beyond possibly yield loss. In fact, because of the large consumer demand for MLC NAND flash for digital cameras, tablets, and smart phones, MLC enjoys economies of scale that give it a cost per bit cost less than half that of SLC.
The read bandwidths between SLC and MLC are comparable: SLC can read a 1KB page in about half the time that MLC can read a 2KB page. In general, the available bandwidth of a solid-state drive is more related to the controller architecture and design than to the speed of the flash. MLC NAND flash technology does pay a price in terms of access speed, however. Access and programming times are two to three times slower than for the single-level design. For many consumer applications, this speed difference will be virtually undetectable.
Endurance
The endurance of SLC NAND flash is 10 to 30 times more than MLC NAND flash (see figure 4). This, and the difference in operating temperature, are the main reasons why SLC NAND flash is considered industrial-grade, and MLC NAND flash is considered consumer-grade. The endurance difference is also generally not a problem in consumer use. For example, a USB drive application that used the 10,000 write/erase cycles would enable the user to completely write and erase the entire contents once per day for 27 years – well beyond the life of the hardware. On the other hand, a data logging application that was constantly writing telemetry or sensor data might completely write the contents of the drive 10 times a day, leading to an endurance of only 2.7 years.
Click image to enlarge
Figure 4: The endurance of SLcC is significantly higher than for MLC, making it a better fit for mission-critical applications.
Error rate
The error rate for MLC NAND flash is 10 to 100 times worse than that of SLC NAND flash and degrades more rapidly with increasing program/erase cycles. This is driven by the very narrow margin between voltage threshold levels in MLC.
There are four principal error mechanisms that affect flash data reliability:
1. Program disturb
2. Read disturb
3. Leakage
4. Charge trapping
Program disturb is caused by the stress to unselected cells in the same erase block as the cell being programmed. These unselected cells can either be adjacent bits on the same page or the corresponding bit on adjacent pages. This voltage stress can cause a small amount of charge to be deposited on the floating gates of these adjoining cells, thus weakly programming them. While not a major problem for SLC NAND flash, the addition of a small amount of charge can cause a shift between the levels in an MLC NAND flash cell. This can be a particular problem with repeated program cycles of adjoining cells. For this reason, well-designed flash controllers program pages sequentially within an erase block. This also explains why MLC NAND flash cannot withstand multiple writes per page.
Read disturb is caused by the voltage difference between the selected page being read and adjacent, unselected pages. This can stress the cells in the adjacent pages and cause a small amount of charge to be transferred to the gate of an erased cell, weakly programming them; again, this is a larger problem for MLC NAND flash cells then SLC cells, since a very small voltage shift can affect the value stored.
Leakage of the charge on the floating gate is the phenomenon that leads to a limit on the data retention time for a cell. The floating gates can lose electrons at a very slow rate, on the order of an electron every week to every month. With the various values in multi-level cells only differentiated by 10s to 100s of electrons, however, this can lead to data retention times that are measured in months, rather than years. This is one of the reasons for the large difference between SLC and MLC data retention and endurance. Leakage is also increased by higher temperatures, which is why MLC NAND flash is generally only appropriate for commercial temperature range applications.
Next: Charge trapping
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S.Gilden
7/17/2012 10:44 AM EDT
FYI: the table discribing the 3-bit MLC has tex errors and pattern "100" is listed twice.
Further , pattern 001 is missing.
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Kristin Lewotsky
7/17/2012 7:39 PM EDT
Good catch--that's what I get for focusing on the text of the article rather than the graphics. I communicated with the author and we are in the process of getting an updated version of the table. Look for a revised version by tomorrow morning. Thank you for your patience and apologies for any confusion.
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cdhmanning
7/17/2012 10:25 PM EDT
Ok, maybe the answer is obvious to me because I have been working closely with NAND for the last 10 or so years...Clearly SLC has wider margins and can thus tolerate more degradation than MLC. Clearly SLC will give a huge reliability advantage.
You can sometimes use MLC parts as if they were SLC parts. Many MLCs write two adjacent pages into the same cells, so if you only write every second page you can sometimes achieve SLC-like reliability in MLC.
This opens up the possibility to do things like using MLC for the cost benefit, storing critical code etc in the fake-SLC area and less critical data/code in the regular MLC area.
NAND is goofy stuff.For example most electronic parts tend to be more reliable at the lower end of their temperature range. NAND, OTOH, is often more prone to errors at lower temperatures.
One failure mechanism you missed is read disturb. Yes, even reading NAND can corrupt data. That is particularly relevant to MLC. This has particular implications for static data like boot code which is typically not rewritten during the lifetime of the product but is read (and slowly corrupted) on every boot cycle.
If you want to ensure that your NAND-based solutions are robust, ensure that the software you are using with it (file systems, boot loaders, etc) have mechanisms to mitigate against the bad side of NAND.
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John Scaramuzzo
7/20/2012 5:50 PM EDT
Charlie, really enjoyed reading your article here. The differences between SLC and MLC Flash have been a topic for discussion for quite some time and as a flash industry professional, we are constantly trying to mimic the advantages of SLC Flash in our MLC-based Solid State Drives. To add to your article, I would also like your readers to consider certain new endurance enhancement technologies that can substantially increase the native endurance and bolster reliability in MLC Flash devices. These types of innovations are blurring the lines between the SLC and MLC output and is making MLC a viable option for even the most write intensive application. Check out this white paper as a great resource for this type of technology on our website: http://smartstoragesys.com/pdfs/WP003_Guardian_Technology.pdf.
-John Scaramuzzo, President, SMART Storage Systems
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elektryk321
7/23/2012 6:48 AM EDT
I have a feeling that explanation of wear mechanism is little wrong. As far I know the problem is not with trapped electrons, electrons could be always moved with force (apropriate voltage) but each time when memory is programmed or erased, move of electrons degrades the isolation properties of oxider.
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