Soft error correction
The continued scaling of complementary metal-oxide semiconductor device technologies has lead to ongoing device shrinkage and a decrease in the operating voltage of the device transistors (Vdd). Scaling has meant denser circuitry overall, thinner silicon (e.g., silicon-on-insulator) in logic applications and less charge on capacitors for volatile memory. Even low-energy alpha particles can flip a memory bit or alter timing in a logic circuit of these smaller, lower voltage chips, making them more susceptible to soft errors. In many cases, these soft errors are self-inflicted because alpha particles are commonly generated in materials adjacent to the chip, solders and in the packaging.
With growing circuit complexity and the converging demands for high reliability and safety, transient errors are no longer restricted to space applications, but are impacting today’s consumer electronic applications, such as biomedical, automotive and networking applications. With this greater susceptibility to soft errors and an increased focus on field reliability, an embedded memory test solution that provides error correcting code (ECC) to detect multi-bit errors and correct transient errors enables designers to meet the target failure-in-time (FIT) rate for their applications.
Test considerations for 3D-ICs
In the quest to integrate more functionality into increasingly smaller form factors with higher performance, lower power, and reduced cost, semiconductors that have traditionally used two-dimensional planes are now taking advantage of the third, vertical dimension. This latest evolution is referred to as a three-dimensional stacked IC, or 3D-IC, and consists of a single package containing a vertical stack of naked dies that are interconnected by means of through-silicon vias (TSVs), as shown in Figure 3.
TSV-based 3D-IC and silicon interposer based 2.5D-IC technologies, shown in Figure 3 and Figure 4, allow the semiconductor industry to continue its pursuit of more functionality, bandwidth, and performance at smaller sizes, power dissipation, and cost; even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive. As with all ICs, 3D-ICs and 2.5D-ICs need to be tested for manufacturing defects.
Figure 3: 3D-ICs with two stacked dies connected by TSVs
Figure 4: 2.5D integration with two dies connected by wires running through a silicon interposer
In general the test content of 3D-ICs is similar to that of conventional 2D ICs, because the same defects can occur during manufacturing, resulting in the same faults, fault models and test patterns. However, the newer 3D-IC technology does have the potential for intra-die defects and TSV interconnects faults that require new tests. Intra-die defects may result from the 3D-IC processing step of wafer thinning. While testing for manufacturing defects in TSV-based 3D-ICs is in the early stages, preliminary results indicate degradation of some I-V characteristics, shifts in device performance, and limited yield losses.
The TSV-based interconnect is a new structure present in 3D-ICs and may be prone to new types of defects. It is therefore necessary to identify these defects and determine how they behave as faults as well as how to model and test for them. Defects might occur in the TSV fabrication or in the TSV bonding between layers of the 3D stack.
Although the actual defect mechanisms are different, the resulting faults for TSV-based interconnects are similar to those associated with wiring interconnects, including opens, shorts, and delay faults. This makes it possible to leverage existing test algorithms to detect TSV interconnect faults through a set of digital test patterns. These test algorithms require full controllability at all interconnect inputs and full observability at all interconnect outputs.
Just as system architects can redesign and re-optimize their system architecture based on the 3D-IC technology, design-for-test (DFT) architects can redesign and re-optimize their DFT architecture, especially as it relates to test resource partitioning, or determining which DFT resource to put into which die. This can be demonstrated with an example of a 3D-IC product consisting of a memory die stacked on top of a logic die. The memory die provider may only make standalone memories, which often do not come with BIST. However the memory I/Os can be accessed by the test equipment and test costs are typically reduced by multi-site testing, or the testing of many memory chips in parallel.
With a 3D-IC chip, die-level testing is conducted as it would be for a standalone memory. On the other hand, the stack test for the same memory die is conducted in a manner similar to testing for an embedded memory, for which BIST is the DFT methodology of choice. To support the use of BIST in these memories, one option is to have the memory die come ‘3D-prepared’ with an on-chip BIST engine, which offers the benefit of ensuring that no proprietary memory test content will have to be released. However, the memory BIST, which is a logic element, might be difficult to implement in the technology of the memory die.
An alternative solution to eliminate this issue is for the memory supplier to provide a description of a memory BIST engine that is implemented in the bottom logic die. In this case, the memory BIST operation is controlled from within the logic die with the stimuli and responses flowing into and out of the memory die through TSV-based interconnects. Any embedded memory test solution used with 3D-IC chips requires complete test, repair and diagnostics support for various external memory types, such as SRAM, DRAM, DDR2, DDR3, LPDDR2, and external memory interfaces such as DDR PHY and Wide I/O memory that might be implemented on the chip, in order to test the external memories and TSV interconnects.